> On Feb 19, 2022, at 1:28 PM, Jon Elson via cctalk <cctalk@classiccmp.org>
> wrote:
>
> On 2/18/22 21:43, ben via cctalk wrote:
>>
>> The 70's was all low scale tech. I suspect it was the high speed/edge rates
>> more the power that kept ECL from common use. Any other views on this topic.
>> Ben, who only had access to RADIO SHACK in the 70's.
>> PS: Still grumbling about buying life time tubes at a big price,
>> just to see all tubes discontinued a year or two later.
>
> Edge rates on pedestrian MECL 10K were not crazy fast. Rise and fall of
> about 1 ns, but the gate propagation delay was ALSO about 1 ns, so that was a
> lot faster than TTL. ECL was very easy to work with, crosstalk was not a
> common issue. But, you HAD to terminate any line over a foot, and better to
> make it 6" to be sure. And, the termination and pulldown resistors ate a LOT
> of power!
I think there are a number of reasons why ECL was niche technology. One is
that TTL was fast enough for most applications. Another is that more people
knew TTL, and ECL requires (some) different design techniques. Yet another is
that higher levels of integration appeared in CMOS but not ECL. Yet another is
that ECL was expensive compared to the alternatives, partly because of the low
integration and partly because of the low volume.
In the mid-1980s (I think) there was a very interesting project at DEC Western
Research Lab to build a custom VSLI ECL processor chip. A lot of amazing
design was done for it. One is power and cooling work; it was estimated to
consume about 100 watts which in that day was utterly unheard of, by a
substantial margin. This was solved by a package with integral heat pipe.
Another issue was the fact that ECL foundries each had their own design rules,
and they were shutting down frequently. So the CAD system needed to be able to
let you specify a design where the fab rules were inputs to the layout
algorithms. The design took great advantage of ECL-specific logic capabilities
like wire OR or stacked pass transistors. I remember that the CAD system let
the designer work at multiple levels in the same chip: at the rectangle level
(for memory arrays), transistor level, gate level, and even write some
constructs as programming language notations. For example a 64-bit register
could be specified as:
for (i = 0; i < 64; i++) { transistor-level schematic of a one-bit
register }
Originally the idea was to use this for a 1 GHz Alpha; I think it ended up
being a 1 GHz MIPS processor. Possibly the project was killed before it quite
finished.
That seems to have been one of the very few examples of ECL going beyond SSI.
The physical possibility existed; the economics did not.
paul
