> On Aug 24, 2021, at 6:34 AM, Diane Bruce <d...@db.net> wrote:
>
> On Mon, Aug 23, 2021 at 09:09:55PM -0400, Paul Koning via cctalk wrote:
>>
>>
>>> On Aug 23, 2021, at 8:38 PM, Tom Stepleton via cctalk
>>> <cctalk@classiccmp.org> wrote:
>>>
>>> Hello,
>>>
>>> For the sake of illustration to folks who are not necessarily used to
>>> thinking about what computers do at the machine code level, I'm interested
>>> in collecting examples of single instructions for any CPU architecture that
>>> are unusually prolific in one way or another.
>>> ...
>>> Although I don't know it well, I suspect VAX will place well in one way or
>>> another.
>>
>> Indeed. Just its addressing modes, with indirection and two separate
>> register indexing operations, are hairy enough. Then consider the decimal
>> arithmetic instructions that might have up to 6 operands.
>
> And who can ever forget the built in CRC instruction?
>
> Amusingly it was demonstrated that many of the CISC instructions were
> faster if one just did them with the 'normal' instruction set.
Not too surprising given that the instruction worked 4 bits at a time while a
reasonable software implementation goes 8 bits at a time.
The more general point is one I learned on the Moto 68040. The task was to
write a fast packet forwarding module (for an FDDI -> Ethernet switch, wihch
ended up being the DECswitch 900). When I studied the instruction timings I
realized the "RISC subset" of the 68040 instruction set and addressing modes
runs in one or two cycles per instruction, while all the other cases take a
great deal more. So I wrote it in the RISC subset, and ended up processing 60k
packets per second, in a 25 MHz processor.
paul
