I especially appreciated he not only offered an opinion - his specific
ideas on where the boarder between RISC and CISC was - but then provided
an analysis of a bunch of processors based on those criteria and an
analysis of the outliers that challenged his criteria. It's a well
thought-out and explained opinion that just doesn't happen often on the
Internet.
I assume from RS/6000, he meant generally the Power gen 1 architecture.
And IBM RT/PC he meant ROMP. I'm pretty sure Alpha was well established
when he wrote the analysis. Would have been nice to see that included.
If I had more time, I'd research it. Maybe SuperH and WE32 as well.
Thanks for sharing! +1
-Alan H.
On 2019-06-12 13:45, Chuck Guzis via cctalk wrote:
On Jun 12, 2019, at 11:59 AM, Liam Proven via cctalk
<cctalk@classiccmp.org> wrote:
Goes a bit over my head but may be of interest:
https://userpages.umbc.edu/~vijay/mashey.on.risc.html
There are fuzzy areas. Consider the ETA 10--a very RISC scalar unit
that pretty much fulfills the criteria laid out, bolted onto a vector
unit (all memory-memory).
