On 2019-Feb-06, at 3:39 PM, Fritz Mueller wrote:
>> On Feb 6, 2019, at 2:24 PM, Brent Hilpert via cctalk <cctalk@classiccmp.org>
>> wrote:
>>
>> Is the schematic available for the memory board at-issue?
>> Curious myself to see what approach for refresh DEC used.
>
> Yes, here:
> http://bitsavers.trailing-edge.com/pdf/dec/pdp11/memory/MP00672_MS11L_engDrw.pdf
>
> There is also a technical manual adjacent, with circuit descriptions.
>
> I will scope this up tonight and take a look!
Mixed up To: fields.
The following was intended to go to the list and was originally sent a moment
before I saw Fritz's message mentioning the 555:
Ha!, simple free-running 555 oscillator generating the refresh cycles
(pdf.pg27).
I suspect there is a mistake in the schematic there:
V-555 more likely connects on the other side of R4 (E5.4-C1-R4, rather
than E5.7-R4-R5)
to make it into the standard 555 astable circuit.
Based on that, calculations indicate that the output from E5 (TP18) should be
around 85 KHz, cycling 6.4 uS high, 5.3 uS low.
So it's generating a refresh cycle every 11.8 uS. With 7 bits used from counter
E43 (128 rows) for full refresh, that's a cell refresh
every 1.5mS which (without having checked the 4116 specs) sounds sensible for a
DRAM from that period.
Note the 555 (E5) is running on +12 or +15V, with a R voltage divider on the
output before driving into TTL.
