Chuck Guzis via cctalk wrote on Tue, 11 Apr 2017 18:05:01 -0700 > On 04/11/2017 04:53 PM, Jecel Assumpcao Jr. via cctalk wrote: > > > I consider the heart of any modern high performance CPU to be a > > dataflow architecture (described as an "out of order execution > > engine") with a hardware to translate the macrocode (CISC or RISC) to > > the dataflow graph and tokens on the fly. > I wouldn't characterize an out-of-order execution scheduler as > "dataflow", at least not in the traditional sense.
I have never seen anybody else, including people whose research in the late 1980s was dataflow architectures, do so either. But I see an engine with 24 "in flight" instructions plus all the register renaming circuits and it sure looks the same to me. > Certainly, nobody that I was aware of ever categorized, say, a CDC 6600 > as a dataflow machine. I was not aware that there had been any out of order implementations after the IBM ACS until the second half of the 1990s. Given Cray's passion for simplicity, I would not expect any of his designs to use o-o-o (specially one as early as the CDC 6600). > At least not in the same sense that I'd categorize a NEC uPD7281 as a > dataflow device. That is the one I am most familiar with, along with the Manchester Dataflow Machine and the MIT Tagged Token machine. An interesting modern dataflow architecture is the TRIPS: https://en.wikipedia.org/wiki/TRIPS_architecture -- Jecel
