I've updated my VHDL 1802 core and COSMAC ELF for a newer FPGA, the Xilinx
Artix 7. As usual, the source code in in the github repository:
https://github.com/brouhaha/cosmac/
On the XC7A100T-1FGG484, which is the slowest speed grade, it meets timing
at 62.5 MHz. Since my 1802 core only needs one clock per machine cycle,
versus 8 for the original CDP1802, it runs at the equivalent of a 500 MHz
CDP1802.
I was actually able to run it at 100 MHz (800 MHz equivalent), but that
doesn't meet timing so there's no guarantee that it will work; it is
"overclocking" the FPGA. I can't really imagine any reason to need an 800
MHz equivalent CDP1802. :-)
It has been tested with a few simple test programs and with CamelForth.
The interrupt support and related instructions are still untested.
Eric
