> > > Also, RISC does not use, or need, microcode. > > > > I'm not sure what you mean by this, but (for example) many POWER > > implementations have microcode (example: the 970/G5, which is descended from > > POWER4). > > What I meant is that I had no idea such things existed. Very curious. > Learn something new every day. What do they use this for?
A number of instructions on G5 processors are broken down into smaller uops which are sequenced, and affect execution flow and instruction level parallelism. The microcode used by the uops is purely internal to the chip and is stored in a sidecar ROM. Part of my optimizing code for G5 systems was to avoid microcoded/cracked instructions as much as possible except where there was no alternative for functionality. The Cell PPU, also Power ISA, also contains microcoded instructions and they have similar penalties. -- ------------------------------------ personal: http://www.cameronkaiser.com/ -- Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckai...@floodgap.com -- I've had a wonderful time, but this wasn't it. -- Groucho Marx -------------
