"When run on the target FPGA, the DSRPA diagnostic completes in slightly less than 9 minutes."
Any idea what the run-time would be a on a real KS10? Lee C. On Tue, Jun 21, 2016 at 1:18 AM, Rob Doyle <radioe...@gmail.com> wrote: > On 6/20/2016 9:07 PM, ben wrote: > >> On 6/20/2016 9:43 PM, Eric Smith wrote: >> >>> On Mon, Jun 20, 2016 at 9:34 PM, ben <bfranc...@jetnet.ab.ca> >>> wrote: >>> >>>> My other pet-peave is that every thing is point and click wizard >>>> for any useful modules. Need a rom module or adder module, point >>>> and click no portable code. >>>> >>> >>> I predominantly use Xilinx, and I don't use much point-and-click >>> at all. I do all my HDL editing in emacs, including instantiating >>> any of the Xilinx-provided IP blocks. My main interaction with the >>> Xilinx software (whether ISE or Vivado) is to click the "generate >>> bitstream" button. It's even possible to do that from the command >>> line or a Makefile, but I haven't bothered. >>> >>> Do you use Static or Dynamic ram with the FPGA's? Ben. >> > > Another example - > > The KS10 FPGA uses 36-bit wide 166 MHz synchronous static RAM (SSRAM) > for main memory. Main memory is as fast as the "Fast ACs". I didn't > bother to implement cache (why bother?) and the Cache Diagnostic still > whines that things that should not be cached are being cached... > > Most good tools can infer about everything from a well written HDL > description. This includes single port and multi-port memory and > includes RAM and ROM. The less tool-specific things that you use, the > more portable your design is. > > The only IP block that I regularly use is a phased-locked-loop block. > > The DEC KS10 used a lot of asynchronous parts (memory, FIFOs/SILOs, > one-shots, delay lines, RC delays, etc) that don't map very well to > modern components - especially FPGAs. I've elected to redesign circuitry > as necessary to use the FPGA resources. Others have elected to retain > the original design as close as possible and accept the consequences. > > The KS10 FPGA is at: > http://www.techtravels.org/?page_id=656 > https://github.com/KS10FPGA/KS10FPGA > > The ALU out of the KS10 FPGA describes a fairly complex circuit > containing memory, registers, multiplexers, shifters, adders, including > an am2901 4-bit slice processor-based ALU all written using generic > Verilog. Also the HDL description has trace tags back to the card, > schematic sheet, and reference designators of the original design - if > you'd like to compare the two. > > The KS10 FPGA ALU design can be viewed at: > https://github.com/KS10FPGA/KS10FPGA/blob/master/fpga/ks10/cpu/alu.v > > Regarding simulation - a full Verilog simulation of the DEC RP06 disk > diagnostic (DSRPA) requires about two and a half weeks to complete on my > fastest computer. That's maybe not suprising because that simulates the > entire CPU running the diagnostic program, memory, the unibus adapters, > the RH11 disk controller, the console terminal, and eight RP06 disk > drives. When run on the target FPGA, the DSRPA diagnostic completes in > slightly less than 9 minutes. > > Rob. > doyle (at) cox (dot) net > -- Lee Courtney +1-650-704-3934 cell
