BUT, there is no I/O supply if the I/O supply is not turned on. The I/O
supply has to be there.

Look, go ahead and ignore me if you like. But I talk to the designers of
this device daily and support hundreds of customers daily. And I
see boards come into the RMA department all the time with blown processors
due to this issue. The power sequencing diagram is there for a reason due
to the multiple voltage rails inside this device. Violate the
power sequencing and you will have issues.


Gerald



On Mon, Feb 24, 2014 at 3:28 PM, <[email protected]> wrote:

> [email protected] wrote:
> > Gerald Coley <[email protected]> wrote:
> > > [-- text/plain, encoding quoted-printable, charset: ISO-8859-1, 56
> lines --]
> > >
> > > Not really. The idea of powering a chip via an I/O pin will
> > > always cause damage. It means voltage as specified by the datasheet of
> > > the component.
> > >
> > I don't aim to 'power' it via the I/O pin!  Maybe that's your way of
> > saying it but it's a very odd way.  The likelihood is that there will
> > be a biggish resistor in series with the input to limit current and
> > there will probably also be some clamping diodes or maybe a buffer
> > amplifier but whatever you do there *cannot* be 'no voltage'.
> >
> > What I'm asking really is what will be tolerated with no problems,
> > every chip spec I have ever seen specifies some sort of minimum, not
> > zero.
> >
> ... and the processor spec *does* tell me!
>
> The limits are specifically stated (as I expected) as follows:-
>
> "Steady state max. voltage at all I/O pins"
> "-0.5 volts to IO supply voltage +0.3 volts"
>
> So, even with power off, some voltage *is* allowed and in fact it
> should be fairly easy to keep the voltage within these limits using
> Schottky diodes for clamping.
>
> *This* is what I've been asking for.
>
> --
> Chris Green
> ยท
>
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