On Sat, Oct 05, 2019 at 12:20:57PM -0400, k...@intricatesoftware.com wrote:
> Various rockchip u-boot 2019.10rc4 aarch64 improvements:
> * u-boot.itb is included in the all target for rockpro64 and
> firefly-rk3399 so remove duplicate make for it.
> * Build rock64-rk3328, except exclude idbloader.img which is broken.
> * Install u-boot-spl-dtb.bin and mkimage for rock64, rockpro64 and
> firefly-rk3399 so that idbloader.img can be created using rkbin TPL
> layer.
> * Provide a script to make idbloader.img from rkbin's TPL layer.
> * For rockpro64 backport PCIe support from 5.3 dtb.
> * For rock64 backport most 4.20 dtb components and additional bug
> fixes.
>
> For rockpro64, I no longer need to have an updated dtb installed
> in the i partition for PCIe to work. Although I am using the
> rkbin TPL layer because the u-boot one doesn't recognize half
> of my memory (other versions of this board dont have this
> problem).
>
> For rock64 the dtb updates corrects the clock bindings so an
> updated dtb is not needed in the i partition as well. However,
> u-boot's TPL layer isn't working yet so the following steps
> are needed to create a usable idbloader.img on a uSD for
> install with miniroot66.fs:
>
> /usr/local/libexec/u-boot/mkidbloader-rkbin rock64-rk3328
> dd if=miniroot66.fs of=/dev/<uSD> bs=1m
> dd if=idbloader.img of=/dev/<uSD> bs=512 seek=64 conv=sync
> dd if=/usr/local/share/u-boot/rock64-rk3328/u-boot.itb \
> of=/dev/<uSD> bs=512 seek=16384 conv=sync
>
> One of the downsides of installing mkimage is the removal of
> PKG_ARCH=*, but we get better support for both rock64 and
> rockpro64 for where rkbin is still needed. I'm not sure how
> well firefly works with the the u-boot TPL layer so it may
> benefit from the ability to build idbloader.img with the
> rkbin TPL layer as well.
>
> Thoughts?
Dropping PKG_ARCH=* isn't something we should do in my opinion. For
example arm package snapshots seem to be made every few months and with
U-Boot 2019.10 final planned for Monday US time there wouldn't be a
package available for arm in time for the final release build.
I think for now you should drop the rk3328/mkimage parts and keep the
rockpro64 dtb change.
>
> PS: My examples include dd with bs=512 with seek's to avoid
> someone from setting a different bs to write faster; and
> conv=sync since this is needed on MacOS and FreeBSD to write
> the partial final blocks. Both of these things tripped me up
> the first time I initially tried to setup my uSD from my Mac.
>
> Index: Makefile
> ===================================================================
> RCS file: /cvs/ports/sysutils/u-boot/Makefile,v
> retrieving revision 1.59
> diff -u -p -u -r1.59 Makefile
> --- Makefile 28 Sep 2019 01:40:24 -0000 1.59
> +++ Makefile 5 Oct 2019 16:15:13 -0000
> @@ -7,6 +7,7 @@ FLAVOR?= arm
>
> COMMENT= U-Boot firmware
> VERSION= 2019.10-rc4
> +REVISION= 0
> DISTNAME= u-boot-${VERSION}
> PKGNAME= u-boot-${FLAVOR}-${VERSION:S/-//}
> FULLPKGNAME= ${PKGNAME}
> @@ -19,7 +20,6 @@ PERMIT_PACKAGE= Yes
>
> MASTER_SITES= https://ftp.denx.de/pub/u-boot/
> EXTRACT_SUFX= .tar.bz2
> -PKG_ARCH= *
>
> BUILD_DEPENDS= devel/bison \
> devel/dtc \
> @@ -36,10 +36,12 @@ MAKE_ENV= KBUILD_VERBOSE=1 \
> PYTHON="${MODPY_BIN}"
>
> .if "${FLAVOR}" == "aarch64"
> +WANTLIB+= c
> BUILD_DEPENDS+= devel/arm-none-eabi/gcc-linaro,aarch64 \
> devel/py-elftools \
> sysutils/arm-trusted-firmware
> MAKE_ENV+= CROSS_COMPILE="aarch64-none-elf-"
> +RK3328_BL31= "${LOCALBASE}/share/arm-trusted-firmware/rk3328-bl31.elf"
> RK3399_BL31= "${LOCALBASE}/share/arm-trusted-firmware/rk3399-bl31.elf"
> SUNXI_BL31= "${LOCALBASE}/share/arm-trusted-firmware/sun50i_a64-bl31.bin"
> .elif "${FLAVOR}" == "arm"
> @@ -68,9 +70,14 @@ BOARDS=\
> mvebu_espressobin-88f3720 \
> mvebu_mcbin-88f8040 \
> qemu_arm64 \
> + rock64-rk3328 \
> rockpro64-rk3399 \
> rpi_3 \
> rpi_4
> +MKIMAGE=\
> + firefly-rk3399 \
> + rock64-rk3328 \
> + rockpro64-rk3399
> .elif "${FLAVOR}" == "arm"
> OMAP=\
> omap4_panda \
> @@ -129,6 +136,7 @@ BOARDS=\
> tinker-rk3288 \
> turris_omnia \
> vexpress_ca15_tc2
> +MKIMAGE=
> .endif
>
> FILES=\
> @@ -143,6 +151,7 @@ FILES=\
> u-boot-with-spl.bin \
> u-boot.itb \
> idbloader.img \
> + spl/u-boot-spl-dtb.bin \
> spl/sunxi-spl.bin \
>
> do-build:
> @@ -151,25 +160,34 @@ do-build:
> mkdir -p build/${BOARD} && \
> ${SETENV} ${MAKE_ENV} ${MAKE_PROGRAM} ${MAKE_FLAGS} \
> O="build/${BOARD}" \
> - -f ${MAKE_FILE} "${BOARD}"_defconfig && \
> + -f ${MAKE_FILE} "${BOARD}"_defconfig
> +.if "${BOARD}" == "firefly-rk3399" || "${BOARD}" == "rockpro64-rk3399"
> + cd ${WRKSRC} && \
> + ${SETENV} ${MAKE_ENV} BL31=${RK3399_BL31} ${MAKE_PROGRAM} \
> + ${MAKE_FLAGS} O="build/${BOARD}" \
> + -f ${MAKE_FILE} ${ALL_TARGET}
> +.elif "${BOARD}" == "rock64-rk3328"
> + cd ${WRKSRC} && \
> + ${SETENV} ${MAKE_ENV} BL31=${RK3328_BL31} ${MAKE_PROGRAM} \
> + ${MAKE_FLAGS} O="build/${BOARD}" \
> + -f ${MAKE_FILE} ${ALL_TARGET}
> + cd ${WRKSRC}/build/${BOARD} && \
> + ${SETENV} ${MAKE_ENV} BL31=${RK3328_BL31} ${MAKE_PROGRAM} \
> + ${MAKE_FLAGS} O="build/${BOARD}" \
> + -f ${MAKE_FILE} u-boot.itb && \
> + rm idbloader.img
> +.else
> + cd ${WRKSRC} && \
> ${SETENV} ${MAKE_ENV} ${MAKE_PROGRAM} ${MAKE_FLAGS} \
> O="build/${BOARD}" \
> -f ${MAKE_FILE} ${ALL_TARGET}
> +.endif
> .if "${BOARD}" == "tinker-rk3288"
> cd ${WRKSRC}/build/${BOARD} && \
> tools/mkimage -n rk3288 -T rksd -d tpl/u-boot-tpl.bin \
> idbloader.img && \
> cat spl/u-boot-spl-dtb.bin >> idbloader.img
> .endif
> -.if "${BOARD}" == "firefly-rk3399" || "${BOARD}" == "rockpro64-rk3399"
> - cd ${WRKSRC}/build/${BOARD} && \
> - ${SETENV} ${MAKE_ENV} BL31=${RK3399_BL31} ${MAKE_PROGRAM} \
> - ${MAKE_FLAGS} O="build/${BOARD}" \
> - -f ${MAKE_FILE} u-boot.itb && \
> - tools/mkimage -n rk3399 -T rksd -d tpl/u-boot-tpl.bin \
> - idbloader.img && \
> - cat spl/u-boot-spl-dtb.bin >> idbloader.img
> -.endif
> .endfor
> .for BOARD in ${SUNXI64}
> cd ${WRKSRC} && \
> @@ -194,5 +212,15 @@ do-install:
> -cd ${WRKSRC}/build/${BOARD} && \
> cp ${FILES} ${PREFIX}/share/u-boot/${BOARD}/
> .endfor
> +.if "${MKIMAGE}" != ""
> + ${INSTALL_DATA_DIR} ${PREFIX}/libexec/u-boot
> + ${INSTALL_PROGRAM} ${FILESDIR}/mkidbloader-rkbin
> ${PREFIX}/libexec/u-boot
> +.for BOARD in ${MKIMAGE}
> + ${INSTALL_DATA_DIR} ${PREFIX}/libexec/u-boot/${BOARD}/
> + -cd ${WRKSRC}/build/${BOARD}/tools && \
> + ${INSTALL_PROGRAM} mkimage \
> + ${PREFIX}/libexec/u-boot/${BOARD}/
> +.endfor
> +.endif
>
> .include <bsd.port.mk>
> Index: files/mkidbloader-rkbin
> ===================================================================
> RCS file: files/mkidbloader-rkbin
> diff -N files/mkidbloader-rkbin
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ files/mkidbloader-rkbin 5 Oct 2019 16:15:13 -0000
> @@ -0,0 +1,54 @@
> +#!/bin/sh -e
> +
> +usage_exit() {
> + echo "Usage: mkidbloader-rkbin <board>"
> + echo " <board> can be one of the following:"
> + echo " rock64-rk3328"
> + echo " rockpro64-rk3399"
> + echo " firefly-rk3399"
> + exit 1
> +}
> +
> +if [[ $# -ne 1 ]]; then
> + echo "ERROR: missing board argument"
> + usage_exit
> +fi
> +
> +BOARD=$1
> +case "$BOARD" in
> + rock64-rk3328)
> + SOC=rk3328
> + RKBIN_TPL=rk3328_ddr_333MHz_v1.16.bin
> + RKBIN_TPL_SHA256=mHGeBGzI8zyjHOk6Vp3D1O4WSY33b54fPRjC9NcXrHA=
> + GITHUB_COMMIT=016471bcfb1a0b1e1269895cb7b6f534813edfdc
> + ;;
> + rockpro64-rk3399)
> + SOC=rk3399
> + RKBIN_TPL=rk3399_ddr_800MHz_v1.23.bin
> + RKBIN_TPL_SHA256=eeufH1rAOUxkjQ321Ta+G+PKb+Le3zOr6INDzjnZHyE=
> + GITHUB_COMMIT=016471bcfb1a0b1e1269895cb7b6f534813edfdc
> + ;;
> + firefly-rk3399)
> + SOC=rk3399
> + RKBIN_TPL=rk3399_ddr_666MHz_v1.23.bin
> + RKBIN_TPL_SHA256=cNb8+lhNyTFTI+WXfs6isrb61u611VbrDHU/MHhBJqY=
> + GITHUB_COMMIT=016471bcfb1a0b1e1269895cb7b6f534813edfdc
> + ;;
> + *)
> + echo "ERROR: unrecognized board $1"
> + usage_exit
> + ;;
> +esac
> +
> +ftp
> https://github.com/rockchip-linux/rkbin/raw/${GITHUB_COMMIT}/bin/rk33/${RKBIN_TPL}
> +if [ "`/bin/sha256 -qb ${RKBIN_TPL}`" != "${RKBIN_TPL_SHA256}" ]; then
> + echo "ERROR: failed sha256 check on ${RKBIN_TPL}"
> + exit 1;
> +fi
> +/usr/local/libexec/u-boot/${BOARD}/mkimage -n ${SOC} -T rksd -d ${RKBIN_TPL}
> idbloader.img.tmp
> +cat /usr/local/share/u-boot/${BOARD}/u-boot-spl-dtb.bin >> idbloader.img.tmp
> +mv idbloader.img.tmp idbloader.img
> +
> +echo "idbloader.img created for ${BOARD}"
> +
> +exit 0
> Index: patches/patch-arch_arm_dts_rk3328-rock64_dts
> ===================================================================
> RCS file: patches/patch-arch_arm_dts_rk3328-rock64_dts
> diff -N patches/patch-arch_arm_dts_rk3328-rock64_dts
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-arch_arm_dts_rk3328-rock64_dts 5 Oct 2019 16:15:13
> -0000
> @@ -0,0 +1,115 @@
> +$OpenBSD$
> +
> +Index: arch/arm/dts/rk3328-rock64.dts
> +--- arch/arm/dts/rk3328-rock64.dts.orig
> ++++ arch/arm/dts/rk3328-rock64.dts
> +@@ -11,7 +11,7 @@
> + compatible = "pine64,rock64", "rockchip,rk3328";
> +
> + chosen {
> +- stdout-path = "serial2:1500000n8";
> ++ stdout-path = "serial2:115200n8";
> + };
> +
> + gmac_clkin: external-gmac-clock {
> +@@ -51,6 +51,23 @@
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + };
> ++
> ++ sound {
> ++ compatible = "audio-graph-card";
> ++ label = "rockchip,rk3328";
> ++ dais = <&spdif_p0>;
> ++ };
> ++
> ++ spdif-dit {
> ++ compatible = "linux,spdif-dit";
> ++ #sound-dai-cells = <0>;
> ++
> ++ port {
> ++ dit_p0_0: endpoint {
> ++ remote-endpoint = <&spdif_p0_0>;
> ++ };
> ++ };
> ++ };
> + };
> +
> + &cpu0 {
> +@@ -98,6 +115,14 @@
> + status = "okay";
> + };
> +
> ++&hdmi {
> ++ status = "okay";
> ++};
> ++
> ++&hdmiphy {
> ++ status = "okay";
> ++};
> ++
> + &i2c1 {
> + status = "okay";
> +
> +@@ -245,6 +270,18 @@
> + status = "okay";
> + };
> +
> ++&spdif {
> ++ pinctrl-0 = <&spdifm0_tx>;
> ++ status = "okay";
> ++ #sound-dai-cells = <0>;
> ++
> ++ spdif_p0: port {
> ++ spdif_p0_0: endpoint {
> ++ remote-endpoint = <&dit_p0_0>;
> ++ };
> ++ };
> ++};
> ++
> + &spi0 {
> + status = "okay";
> +
> +@@ -257,10 +294,28 @@
> + };
> + };
> +
> ++&tsadc {
> ++ rockchip,hw-tshut-mode = <0>;
> ++ rockchip,hw-tshut-polarity = <0>;
> ++ status = "okay";
> ++};
> ++
> + &uart2 {
> + status = "okay";
> + };
> +
> ++&u2phy {
> ++ status = "okay";
> ++
> ++ u2phy_host: host-port {
> ++ status = "okay";
> ++ };
> ++
> ++ u2phy_otg: otg-port {
> ++ status = "okay";
> ++ };
> ++};
> ++
> + &usb20_otg {
> + dr_mode = "host";
> + status = "okay";
> +@@ -271,5 +326,13 @@
> + };
> +
> + &usb_host0_ohci {
> ++ status = "okay";
> ++};
> ++
> ++&vop {
> ++ status = "okay";
> ++};
> ++
> ++&vop_mmu {
> + status = "okay";
> + };
> Index: patches/patch-arch_arm_dts_rk3328_dtsi
> ===================================================================
> RCS file: patches/patch-arch_arm_dts_rk3328_dtsi
> diff -N patches/patch-arch_arm_dts_rk3328_dtsi
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-arch_arm_dts_rk3328_dtsi 5 Oct 2019 16:15:13 -0000
> @@ -0,0 +1,2008 @@
> +$OpenBSD$
> +
> +Index: arch/arm/dts/rk3328.dtsi
> +--- arch/arm/dts/rk3328.dtsi.orig
> ++++ arch/arm/dts/rk3328.dtsi
> +@@ -1,6 +1,6 @@
> +-// SPDX-License-Identifier: GPL-2.0+
> ++// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> + /*
> +- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> ++ * Copyright (c) 2017 Fuzhou Rockchip Electronics Co., Ltd
> + */
> +
> + #include <dt-bindings/clock/rk3328-cru.h>
> +@@ -26,7 +26,7 @@
> + i2c3 = &i2c3;
> + mmc0 = &emmc;
> + mmc1 = &sdmmc;
> +- mmc2 = &sdmmc_ext;
> ++ mmc2 = &usb_host0_ehci;
> + };
> +
> + cpus {
> +@@ -37,67 +37,101 @@
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x0>;
> ++ clocks = <&cru ARMCLK>;
> + enable-method = "psci";
> +-// clocks = <&cru ARMCLK>;
> ++ next-level-cache = <&l2>;
> + operating-points-v2 = <&cpu0_opp_table>;
> + };
> ++
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x1>;
> ++ clocks = <&cru ARMCLK>;
> + enable-method = "psci";
> ++ next-level-cache = <&l2>;
> ++ operating-points-v2 = <&cpu0_opp_table>;
> + };
> ++
> + cpu2: cpu@2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x2>;
> ++ clocks = <&cru ARMCLK>;
> + enable-method = "psci";
> ++ next-level-cache = <&l2>;
> ++ operating-points-v2 = <&cpu0_opp_table>;
> + };
> ++
> + cpu3: cpu@3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a53", "arm,armv8";
> + reg = <0x0 0x3>;
> ++ clocks = <&cru ARMCLK>;
> + enable-method = "psci";
> ++ next-level-cache = <&l2>;
> ++ operating-points-v2 = <&cpu0_opp_table>;
> + };
> ++
> ++ l2: l2-cache0 {
> ++ compatible = "cache";
> ++ };
> + };
> +
> + cpu0_opp_table: opp_table0 {
> + compatible = "operating-points-v2";
> + opp-shared;
> +
> +- opp@408000000 {
> ++ opp-408000000 {
> + opp-hz = /bits/ 64 <408000000>;
> + opp-microvolt = <950000>;
> + clock-latency-ns = <40000>;
> + opp-suspend;
> + };
> +- opp@600000000 {
> ++ opp-600000000 {
> + opp-hz = /bits/ 64 <600000000>;
> + opp-microvolt = <950000>;
> + clock-latency-ns = <40000>;
> + };
> +- opp@816000000 {
> ++ opp-816000000 {
> + opp-hz = /bits/ 64 <816000000>;
> + opp-microvolt = <1000000>;
> + clock-latency-ns = <40000>;
> + };
> +- opp@1008000000 {
> ++ opp-1008000000 {
> + opp-hz = /bits/ 64 <1008000000>;
> + opp-microvolt = <1100000>;
> + clock-latency-ns = <40000>;
> + };
> +- opp@1200000000 {
> ++ opp-1200000000 {
> + opp-hz = /bits/ 64 <1200000000>;
> + opp-microvolt = <1225000>;
> + clock-latency-ns = <40000>;
> + };
> +- opp@1296000000 {
> ++ opp-1296000000 {
> + opp-hz = /bits/ 64 <1296000000>;
> + opp-microvolt = <1300000>;
> + clock-latency-ns = <40000>;
> + };
> + };
> +
> ++ amba {
> ++ compatible = "simple-bus";
> ++ #address-cells = <2>;
> ++ #size-cells = <2>;
> ++ ranges;
> ++
> ++ dmac: dmac@ff1f0000 {
> ++ compatible = "arm,pl330", "arm,primecell";
> ++ reg = <0x0 0xff1f0000 0x0 0x4000>;
> ++ interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru ACLK_DMAC>;
> ++ clock-names = "apb_pclk";
> ++ #dma-cells = <1>;
> ++ };
> ++ };
> ++
> + arm-pmu {
> + compatible = "arm,cortex-a53-pmu";
> + interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
> +@@ -107,8 +141,13 @@
> + interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
> + };
> +
> ++ display_subsystem: display-subsystem {
> ++ compatible = "rockchip,display-subsystem";
> ++ ports = <&vop_out>;
> ++ };
> ++
> + psci {
> +- compatible = "arm,psci-1.0";
> ++ compatible = "arm,psci-1.0", "arm,psci-0.2";
> + method = "smc";
> + };
> +
> +@@ -134,7 +173,6 @@
> + clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + dmas = <&dmac 11>, <&dmac 12>;
> +- #dma-cells = <2>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +@@ -146,7 +184,6 @@
> + clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + dmas = <&dmac 14>, <&dmac 15>;
> +- #dma-cells = <2>;
> + dma-names = "tx", "rx";
> + status = "disabled";
> + };
> +@@ -158,16 +195,7 @@
> + clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
> + clock-names = "i2s_clk", "i2s_hclk";
> + dmas = <&dmac 0>, <&dmac 1>;
> +- #dma-cells = <2>;
> + dma-names = "tx", "rx";
> +- pinctrl-names = "default", "sleep";
> +- pinctrl-0 = <&i2s2m0_mclk
> +- &i2s2m0_sclk
> +- &i2s2m0_lrcktx
> +- &i2s2m0_lrckrx
> +- &i2s2m0_sdo
> +- &i2s2m0_sdi>;
> +- pinctrl-1 = <&i2s2m0_sleep>;
> + status = "disabled";
> + };
> +
> +@@ -178,21 +206,49 @@
> + clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
> + clock-names = "mclk", "hclk";
> + dmas = <&dmac 10>;
> +- #dma-cells = <1>;
> + dma-names = "tx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spdifm2_tx>;
> + status = "disabled";
> + };
> +
> ++ pdm: pdm@ff040000 {
> ++ compatible = "rockchip,pdm";
> ++ reg = <0x0 0xff040000 0x0 0x1000>;
> ++ clocks = <&cru SCLK_PDM>, <&cru HCLK_PDM>;
> ++ clock-names = "pdm_clk", "pdm_hclk";
> ++ dmas = <&dmac 16>;
> ++ dma-names = "rx";
> ++ pinctrl-names = "default", "sleep";
> ++ pinctrl-0 = <&pdmm0_clk
> ++ &pdmm0_sdi0
> ++ &pdmm0_sdi1
> ++ &pdmm0_sdi2
> ++ &pdmm0_sdi3>;
> ++ pinctrl-1 = <&pdmm0_clk_sleep
> ++ &pdmm0_sdi0_sleep
> ++ &pdmm0_sdi1_sleep
> ++ &pdmm0_sdi2_sleep
> ++ &pdmm0_sdi3_sleep>;
> ++ status = "disabled";
> ++ };
> ++
> + grf: syscon@ff100000 {
> + compatible = "rockchip,rk3328-grf", "syscon", "simple-mfd";
> + reg = <0x0 0xff100000 0x0 0x1000>;
> ++ #address-cells = <1>;
> ++ #size-cells = <1>;
> +
> + io_domains: io-domains {
> + compatible = "rockchip,rk3328-io-voltage-domain";
> + status = "disabled";
> + };
> ++
> ++ grf_gpio: grf-gpio {
> ++ compatible = "rockchip,rk3328-grf-gpio";
> ++ gpio-controller;
> ++ #gpio-cells = <2>;
> ++ };
> + };
> +
> + uart0: serial@ff110000 {
> +@@ -201,12 +257,12 @@
> + interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
> + clock-names = "baudclk", "apb_pclk";
> +- reg-shift = <2>;
> +- reg-io-width = <4>;
> + dmas = <&dmac 2>, <&dmac 3>;
> +- #dma-cells = <2>;
> ++ dma-names = "tx", "rx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart0_xfer &uart0_cts &uart0_rts>;
> ++ reg-io-width = <4>;
> ++ reg-shift = <2>;
> + status = "disabled";
> + };
> +
> +@@ -215,13 +271,13 @@
> + reg = <0x0 0xff120000 0x0 0x100>;
> + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
> +- clock-names = "sclk_uart", "pclk_uart";
> +- reg-shift = <2>;
> +- reg-io-width = <4>;
> ++ clock-names = "baudclk", "apb_pclk";
> + dmas = <&dmac 4>, <&dmac 5>;
> +- #dma-cells = <2>;
> ++ dma-names = "tx", "rx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart1_xfer &uart1_cts &uart1_rts>;
> ++ reg-io-width = <4>;
> ++ reg-shift = <2>;
> + status = "disabled";
> + };
> +
> +@@ -231,22 +287,17 @@
> + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
> + clock-names = "baudclk", "apb_pclk";
> +- reg-shift = <2>;
> +- reg-io-width = <4>;
> + dmas = <&dmac 6>, <&dmac 7>;
> +- #dma-cells = <2>;
> ++ dma-names = "tx", "rx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&uart2m1_xfer>;
> ++ reg-io-width = <4>;
> ++ reg-shift = <2>;
> + status = "disabled";
> + };
> +
> +- pmu: power-management@ff140000 {
> +- compatible = "rockchip,rk3328-pmu", "syscon", "simple-mfd";
> +- reg = <0x0 0xff140000 0x0 0x1000>;
> +- };
> +-
> + i2c0: i2c@ff150000 {
> +- compatible = "rockchip,rk3328-i2c";
> ++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
> + reg = <0x0 0xff150000 0x0 0x1000>;
> + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> +@@ -259,7 +310,7 @@
> + };
> +
> + i2c1: i2c@ff160000 {
> +- compatible = "rockchip,rk3328-i2c";
> ++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
> + reg = <0x0 0xff160000 0x0 0x1000>;
> + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> +@@ -272,7 +323,7 @@
> + };
> +
> + i2c2: i2c@ff170000 {
> +- compatible = "rockchip,rk3328-i2c";
> ++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
> + reg = <0x0 0xff170000 0x0 0x1000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> +@@ -285,7 +336,7 @@
> + };
> +
> + i2c3: i2c@ff180000 {
> +- compatible = "rockchip,rk3328-i2c";
> ++ compatible = "rockchip,rk3328-i2c", "rockchip,rk3399-i2c";
> + reg = <0x0 0xff180000 0x0 0x1000>;
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + #address-cells = <1>;
> +@@ -306,7 +357,6 @@
> + clocks = <&cru SCLK_SPI>, <&cru PCLK_SPI>;
> + clock-names = "spiclk", "apb_pclk";
> + dmas = <&dmac 8>, <&dmac 9>;
> +- #dma-cells = <2>;
> + dma-names = "tx", "rx";
> + pinctrl-names = "default";
> + pinctrl-0 = <&spi0m2_clk &spi0m2_tx &spi0m2_rx &spi0m2_cs0>;
> +@@ -317,28 +367,100 @@
> + compatible = "snps,dw-wdt";
> + reg = <0x0 0xff1a0000 0x0 0x100>;
> + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
> ++ };
> ++
> ++ pwm0: pwm@ff1b0000 {
> ++ compatible = "rockchip,rk3328-pwm";
> ++ reg = <0x0 0xff1b0000 0x0 0x10>;
> ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
> ++ clock-names = "pwm", "pclk";
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&pwm0_pin>;
> ++ #pwm-cells = <3>;
> + status = "disabled";
> + };
> +
> +- amba {
> +- compatible = "simple-bus";
> +- #address-cells = <2>;
> +- #size-cells = <2>;
> +- ranges;
> ++ pwm1: pwm@ff1b0010 {
> ++ compatible = "rockchip,rk3328-pwm";
> ++ reg = <0x0 0xff1b0010 0x0 0x10>;
> ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
> ++ clock-names = "pwm", "pclk";
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&pwm1_pin>;
> ++ #pwm-cells = <3>;
> ++ status = "disabled";
> ++ };
> +
> +- dmac: dmac@ff1f0000 {
> +- compatible = "arm,pl330", "arm,primecell";
> +- reg = <0x0 0xff1f0000 0x0 0x4000>;
> +- interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
> +- <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
> +- clocks = <&cru ACLK_DMAC>;
> +- clock-names = "apb_pclk";
> +- #dma-cells = <1>;
> ++ pwm2: pwm@ff1b0020 {
> ++ compatible = "rockchip,rk3328-pwm";
> ++ reg = <0x0 0xff1b0020 0x0 0x10>;
> ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
> ++ clock-names = "pwm", "pclk";
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&pwm2_pin>;
> ++ #pwm-cells = <3>;
> ++ status = "disabled";
> ++ };
> ++
> ++ pwm3: pwm@ff1b0030 {
> ++ compatible = "rockchip,rk3328-pwm";
> ++ reg = <0x0 0xff1b0030 0x0 0x10>;
> ++ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru SCLK_PWM>, <&cru PCLK_PWM>;
> ++ clock-names = "pwm", "pclk";
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&pwmir_pin>;
> ++ #pwm-cells = <3>;
> ++ status = "disabled";
> ++ };
> ++
> ++ tsadc: tsadc@ff250000 {
> ++ compatible = "rockchip,rk3328-tsadc";
> ++ reg = <0x0 0xff250000 0x0 0x100>;
> ++ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> ++ assigned-clocks = <&cru SCLK_TSADC>;
> ++ assigned-clock-rates = <50000>;
> ++ clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
> ++ clock-names = "tsadc", "apb_pclk";
> ++ pinctrl-names = "init", "default", "sleep";
> ++ pinctrl-0 = <&otp_gpio>;
> ++ pinctrl-1 = <&otp_out>;
> ++ pinctrl-2 = <&otp_gpio>;
> ++ resets = <&cru SRST_TSADC>;
> ++ reset-names = "tsadc-apb";
> ++ rockchip,grf = <&grf>;
> ++ rockchip,hw-tshut-temp = <100000>;
> ++ #thermal-sensor-cells = <1>;
> ++ status = "disabled";
> ++ };
> ++
> ++ efuse: efuse@ff260000 {
> ++ compatible = "rockchip,rk3328-efuse";
> ++ reg = <0x0 0xff260000 0x0 0x50>;
> ++ #address-cells = <1>;
> ++ #size-cells = <1>;
> ++ clocks = <&cru SCLK_EFUSE>;
> ++ clock-names = "pclk_efuse";
> ++ rockchip,efuse-size = <0x20>;
> ++
> ++ /* Data cells */
> ++ efuse_id: id@7 {
> ++ reg = <0x07 0x10>;
> + };
> ++ cpu_leakage: cpu-leakage@17 {
> ++ reg = <0x17 0x1>;
> ++ };
> ++ logic_leakage: logic-leakage@19 {
> ++ reg = <0x19 0x1>;
> ++ };
> ++ efuse_cpu_version: cpu-version@1a {
> ++ reg = <0x1a 0x1>;
> ++ bits = <3 3>;
> ++ };
> + };
> +
> +- saradc: saradc@ff280000 {
> +- compatible = "rockchip,rk3328-saradc", "rockchip,saradc";
> ++ saradc: adc@ff280000 {
> ++ compatible = "rockchip,rk3328-saradc", "rockchip,rk3399-saradc";
> + reg = <0x0 0xff280000 0x0 0x100>;
> + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
> + #io-channel-cells = <1>;
> +@@ -349,6 +471,145 @@
> + status = "disabled";
> + };
> +
> ++ gpu: gpu@ff300000 {
> ++ compatible = "rockchip,rk3328-mali", "arm,mali-450";
> ++ reg = <0x0 0xff300000 0x0 0x40000>;
> ++ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "gp",
> ++ "gpmmu",
> ++ "pp",
> ++ "pp0",
> ++ "ppmmu0",
> ++ "pp1",
> ++ "ppmmu1";
> ++ clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
> ++ clock-names = "bus", "core";
> ++ resets = <&cru SRST_GPU_A>;
> ++ };
> ++
> ++ h265e_mmu: iommu@ff330200 {
> ++ compatible = "rockchip,iommu";
> ++ reg = <0x0 0xff330200 0 0x100>;
> ++ interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "h265e_mmu";
> ++ clocks = <&cru ACLK_H265>, <&cru PCLK_H265>;
> ++ clock-names = "aclk", "iface";
> ++ #iommu-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> ++ vepu_mmu: iommu@ff340800 {
> ++ compatible = "rockchip,iommu";
> ++ reg = <0x0 0xff340800 0x0 0x40>;
> ++ interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "vepu_mmu";
> ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> ++ clock-names = "aclk", "iface";
> ++ #iommu-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> ++ vpu_mmu: iommu@ff350800 {
> ++ compatible = "rockchip,iommu";
> ++ reg = <0x0 0xff350800 0x0 0x40>;
> ++ interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "vpu_mmu";
> ++ clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
> ++ clock-names = "aclk", "iface";
> ++ #iommu-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> ++ rkvdec_mmu: iommu@ff360480 {
> ++ compatible = "rockchip,iommu";
> ++ reg = <0x0 0xff360480 0x0 0x40>, <0x0 0xff3604c0 0x0 0x40>;
> ++ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "rkvdec_mmu";
> ++ clocks = <&cru ACLK_RKVDEC>, <&cru HCLK_RKVDEC>;
> ++ clock-names = "aclk", "iface";
> ++ #iommu-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> ++ vop: vop@ff370000 {
> ++ compatible = "rockchip,rk3328-vop";
> ++ reg = <0x0 0xff370000 0x0 0x3efc>;
> ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru ACLK_VOP>, <&cru DCLK_LCDC>, <&cru HCLK_VOP>;
> ++ clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
> ++ resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>, <&cru
> SRST_VOP_D>;
> ++ reset-names = "axi", "ahb", "dclk";
> ++ iommus = <&vop_mmu>;
> ++ status = "disabled";
> ++
> ++ vop_out: port {
> ++ #address-cells = <1>;
> ++ #size-cells = <0>;
> ++
> ++ vop_out_hdmi: endpoint@0 {
> ++ reg = <0>;
> ++ remote-endpoint = <&hdmi_in_vop>;
> ++ };
> ++ };
> ++ };
> ++
> ++ vop_mmu: iommu@ff373f00 {
> ++ compatible = "rockchip,iommu";
> ++ reg = <0x0 0xff373f00 0x0 0x100>;
> ++ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "vop_mmu";
> ++ clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
> ++ clock-names = "aclk", "iface";
> ++ #iommu-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> ++ hdmi: hdmi@ff3c0000 {
> ++ compatible = "rockchip,rk3328-dw-hdmi";
> ++ reg = <0x0 0xff3c0000 0x0 0x20000>;
> ++ reg-io-width = <4>;
> ++ interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru PCLK_HDMI>,
> ++ <&cru SCLK_HDMI_SFC>;
> ++ clock-names = "iahb",
> ++ "isfr";
> ++ phys = <&hdmiphy>;
> ++ phy-names = "hdmi";
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&hdmi_cec &hdmii2c_xfer &hdmi_hpd>;
> ++ rockchip,grf = <&grf>;
> ++ status = "disabled";
> ++
> ++ ports {
> ++ hdmi_in: port {
> ++ hdmi_in_vop: endpoint {
> ++ remote-endpoint = <&vop_out_hdmi>;
> ++ };
> ++ };
> ++ };
> ++ };
> ++
> ++ hdmiphy: phy@ff430000 {
> ++ compatible = "rockchip,rk3328-hdmi-phy";
> ++ reg = <0x0 0xff430000 0x0 0x10000>;
> ++ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru PCLK_HDMIPHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
> ++ clock-names = "sysclk", "refoclk", "refpclk";
> ++ clock-output-names = "hdmi_phy";
> ++ #clock-cells = <0>;
> ++ nvmem-cells = <&efuse_cpu_version>;
> ++ nvmem-cell-names = "cpu-version";
> ++ #phy-cells = <0>;
> ++ status = "disabled";
> ++ };
> ++
> + cru: clock-controller@ff440000 {
> + compatible = "rockchip,rk3328-cru", "rockchip,cru", "syscon";
> + reg = <0x0 0xff440000 0x0 0x1000>;
> +@@ -356,6 +617,12 @@
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + assigned-clocks =
> ++ /*
> ++ * CPLL should run at 1200, but that is to high for
> ++ * the initial dividers of most of its children.
> ++ * We need set cpll child clk div first,
> ++ * and then set the cpll frequency.
> ++ */
> + <&cru DCLK_LCDC>, <&cru SCLK_PDM>,
> + <&cru SCLK_RTC32K>, <&cru SCLK_UART0>,
> + <&cru SCLK_UART1>, <&cru SCLK_UART2>,
> +@@ -371,15 +638,7 @@
> + <&cru ACLK_BUS_PRE>, <&cru HCLK_BUS_PRE>,
> + <&cru PCLK_BUS_PRE>, <&cru ACLK_PERI_PRE>,
> + <&cru HCLK_PERI>, <&cru PCLK_PERI>,
> +- <&cru ACLK_VIO_PRE>, <&cru HCLK_VIO_PRE>,
> +- <&cru ACLK_RGA_PRE>, <&cru SCLK_RGA>,
> +- <&cru ACLK_VOP_PRE>, <&cru ACLK_RKVDEC_PRE>,
> +- <&cru ACLK_RKVENC>, <&cru ACLK_VPU_PRE>,
> +- <&cru SCLK_VDEC_CABAC>, <&cru SCLK_VDEC_CORE>,
> +- <&cru SCLK_VENC_CORE>, <&cru SCLK_VENC_DSP>,
> +- <&cru SCLK_EFUSE>, <&cru PCLK_DDR>,
> +- <&cru ACLK_GMAC>, <&cru PCLK_GMAC>,
> +- <&cru SCLK_RTC32K>, <&cru SCLK_USB3OTG_SUSPEND>;
> ++ <&cru SCLK_RTC32K>;
> + assigned-clock-parents =
> + <&cru HDMIPHY>, <&cru PLL_APLL>,
> + <&cru PLL_GPLL>, <&xin24m>,
> +@@ -400,55 +659,82 @@
> + <150000000>, <75000000>,
> + <75000000>, <150000000>,
> + <75000000>, <75000000>,
> +- <300000000>, <100000000>,
> +- <300000000>, <200000000>,
> +- <400000000>, <500000000>,
> +- <200000000>, <300000000>,
> +- <300000000>, <250000000>,
> +- <200000000>, <100000000>,
> +- <24000000>, <100000000>,
> +- <150000000>, <50000000>,
> +- <32768>, <32768>;
> ++ <32768>;
> + };
> +
> +- sdmmc: rksdmmc@ff500000 {
> ++ usb2phy_grf: syscon@ff450000 {
> ++ compatible = "rockchip,rk3328-usb2phy-grf", "syscon",
> ++ "simple-mfd";
> ++ reg = <0x0 0xff450000 0x0 0x10000>;
> ++ #address-cells = <1>;
> ++ #size-cells = <1>;
> ++
> ++ u2phy: usb2-phy@100 {
> ++ compatible = "rockchip,rk3328-usb2phy";
> ++ reg = <0x100 0x10>;
> ++ clocks = <&xin24m>;
> ++ clock-names = "phyclk";
> ++ clock-output-names = "usb480m_phy";
> ++ #clock-cells = <0>;
> ++ assigned-clocks = <&cru USB480M>;
> ++ assigned-clock-parents = <&u2phy>;
> ++ status = "disabled";
> ++
> ++ u2phy_otg: otg-port {
> ++ #phy-cells = <0>;
> ++ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
> ++ <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "otg-bvalid", "otg-id",
> ++ "linestate";
> ++ status = "disabled";
> ++ };
> ++
> ++ u2phy_host: host-port {
> ++ #phy-cells = <0>;
> ++ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "linestate";
> ++ status = "disabled";
> ++ };
> ++ };
> ++ };
> ++
> ++ sdmmc: dwmmc@ff500000 {
> + compatible = "rockchip,rk3328-dw-mshc",
> "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xff500000 0x0 0x4000>;
> +- max-frequency = <150000000>;
> +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
> +- clock-names = "biu", "ciu";
> +- fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
> ++ <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
> ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> ++ fifo-depth = <0x100>;
> + status = "disabled";
> + };
> +
> + sdio: dwmmc@ff510000 {
> + compatible = "rockchip,rk3328-dw-mshc",
> "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xff510000 0x0 0x4000>;
> +- max-frequency = <150000000>;
> ++ interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
> + <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
> +- clock-names = "biu", "ciu", "ciu_drv", "ciu_sample";
> ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> + fifo-depth = <0x100>;
> +- interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
> + status = "disabled";
> + };
> +
> +- emmc: rksdmmc@ff520000 {
> ++ emmc: dwmmc@ff520000 {
> + compatible = "rockchip,rk3328-dw-mshc",
> "rockchip,rk3288-dw-mshc";
> + reg = <0x0 0xff520000 0x0 0x4000>;
> +- max-frequency = <150000000>;
> +- clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>;
> +- clock-names = "biu", "ciu";
> +- fifo-depth = <0x100>;
> + interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
> ++ <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
> ++ clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
> ++ fifo-depth = <0x100>;
> + status = "disabled";
> + };
> +
> + gmac2io: ethernet@ff540000 {
> + compatible = "rockchip,rk3328-gmac";
> + reg = <0x0 0xff540000 0x0 0x10000>;
> +- rockchip,grf = <&grf>;
> + interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "macirq";
> + clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_RX>,
> +@@ -461,21 +747,45 @@
> + "pclk_mac";
> + resets = <&cru SRST_GMAC2IO_A>;
> + reset-names = "stmmaceth";
> ++ rockchip,grf = <&grf>;
> + status = "disabled";
> + };
> +
> +- usb_host0_ehci: usb@ff5c0000 {
> +- compatible = "generic-ehci";
> +- reg = <0x0 0xff5c0000 0x0 0x10000>;
> +- interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> ++ gmac2phy: ethernet@ff550000 {
> ++ compatible = "rockchip,rk3328-gmac";
> ++ reg = <0x0 0xff550000 0x0 0x10000>;
> ++ rockchip,grf = <&grf>;
> ++ interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
> ++ interrupt-names = "macirq";
> ++ clocks = <&cru SCLK_MAC2PHY_SRC>, <&cru SCLK_MAC2PHY_RXTX>,
> ++ <&cru SCLK_MAC2PHY_RXTX>, <&cru SCLK_MAC2PHY_REF>,
> ++ <&cru ACLK_MAC2PHY>, <&cru PCLK_MAC2PHY>,
> ++ <&cru SCLK_MAC2PHY_OUT>;
> ++ clock-names = "stmmaceth", "mac_clk_rx",
> ++ "mac_clk_tx", "clk_mac_ref",
> ++ "aclk_mac", "pclk_mac",
> ++ "clk_macphy";
> ++ resets = <&cru SRST_GMAC2PHY_A>, <&cru SRST_MACPHY>;
> ++ reset-names = "stmmaceth", "mac-phy";
> ++ phy-mode = "rmii";
> ++ phy-handle = <&phy>;
> + status = "disabled";
> +- };
> +
> +- usb_host0_ohci: usb@ff5d0000 {
> +- compatible = "generic-ohci";
> +- reg = <0x0 0xff5d0000 0x0 0x10000>;
> +- interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> +- status = "disabled";
> ++ mdio {
> ++ compatible = "snps,dwmac-mdio";
> ++ #address-cells = <1>;
> ++ #size-cells = <0>;
> ++
> ++ phy: phy@0 {
> ++ compatible = "ethernet-phy-id1234.d400",
> "ethernet-phy-ieee802.3-c22";
> ++ reg = <0>;
> ++ clocks = <&cru SCLK_MAC2PHY_OUT>;
> ++ resets = <&cru SRST_MACPHY>;
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&fephyled_rxm1 &fephyled_linkm1>;
> ++ phy-is-integrated;
> ++ };
> ++ };
> + };
> +
> + usb20_otg: usb@ff580000 {
> +@@ -483,23 +793,41 @@
> + "snps,dwc2";
> + reg = <0x0 0xff580000 0x0 0x40000>;
> + interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
> +- hnp-srp-disable;
> ++ clocks = <&cru HCLK_OTG>;
> ++ clock-names = "otg";
> + dr_mode = "otg";
> ++ g-np-tx-fifo-size = <16>;
> ++ g-rx-fifo-size = <280>;
> ++ g-tx-fifo-size = <256 128 128 64 32 16>;
> ++ g-use-dma;
> ++ phys = <&u2phy_otg>;
> ++ phy-names = "usb2-phy";
> + status = "disabled";
> + };
> +
> +- sdmmc_ext: rksdmmc@ff5f0000 {
> +- compatible = "rockchip,rk3328-dw-mshc",
> "rockchip,rk3288-dw-mshc";
> +- reg = <0x0 0xff5f0000 0x0 0x4000>;
> +- max-frequency = <150000000>;
> +- clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>;
> +- clock-names = "biu", "ciu";
> +- fifo-depth = <0x100>;
> +- interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
> ++ usb_host0_ehci: usb@ff5c0000 {
> ++ compatible = "generic-ehci";
> ++ reg = <0x0 0xff5c0000 0x0 0x10000>;
> ++ interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru HCLK_HOST0>, <&u2phy>;
> ++ clock-names = "usbhost", "utmi";
> ++ phys = <&u2phy_host>;
> ++ phy-names = "usb";
> + status = "disabled";
> + };
> +
> +- gic: interrupt-controller@ffb70000 {
> ++ usb_host0_ohci: usb@ff5d0000 {
> ++ compatible = "generic-ohci";
> ++ reg = <0x0 0xff5d0000 0x0 0x10000>;
> ++ interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
> ++ clocks = <&cru HCLK_HOST0>, <&u2phy>;
> ++ clock-names = "usbhost", "utmi";
> ++ phys = <&u2phy_host>;
> ++ phy-names = "usb";
> ++ status = "disabled";
> ++ };
> ++
> ++ gic: interrupt-controller@ff811000 {
> + compatible = "arm,gic-400";
> + #interrupt-cells = <3>;
> + #address-cells = <0>;
> +@@ -647,812 +975,721 @@
> +
> + i2c0 {
> + i2c0_xfer: i2c0-xfer {
> +- rockchip,pins =
> +- <2 24 RK_FUNC_1 &pcfg_pull_none>,
> +- <2 25 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PD0 1 &pcfg_pull_none>,
> ++ <2 RK_PD1 1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c1 {
> + i2c1_xfer: i2c1-xfer {
> +- rockchip,pins =
> +- <2 4 RK_FUNC_2 &pcfg_pull_none>,
> +- <2 5 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA4 2 &pcfg_pull_none>,
> ++ <2 RK_PA5 2 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c2 {
> + i2c2_xfer: i2c2-xfer {
> +- rockchip,pins =
> +- <2 13 RK_FUNC_1 &pcfg_pull_none>,
> +- <2 14 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>,
> ++ <2 RK_PB6 1 &pcfg_pull_none>;
> + };
> + };
> +
> + i2c3 {
> + i2c3_xfer: i2c3-xfer {
> +- rockchip,pins =
> +- <0 5 RK_FUNC_2 &pcfg_pull_none>,
> +- <0 6 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PA5 2 &pcfg_pull_none>,
> ++ <0 RK_PA6 2 &pcfg_pull_none>;
> + };
> + i2c3_gpio: i2c3-gpio {
> + rockchip,pins =
> +- <0 5 RK_FUNC_GPIO &pcfg_pull_none>,
> +- <0 6 RK_FUNC_GPIO &pcfg_pull_none>;
> ++ <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>,
> ++ <0 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> + };
> +
> + hdmi_i2c {
> + hdmii2c_xfer: hdmii2c-xfer {
> ++ rockchip,pins = <0 RK_PA5 1 &pcfg_pull_none>,
> ++ <0 RK_PA6 1 &pcfg_pull_none>;
> ++ };
> ++ };
> ++
> ++ pdm-0 {
> ++ pdmm0_clk: pdmm0-clk {
> ++ rockchip,pins = <2 RK_PC2 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_fsync: pdmm0-fsync {
> ++ rockchip,pins = <2 RK_PC7 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_sdi0: pdmm0-sdi0 {
> ++ rockchip,pins = <2 RK_PC3 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_sdi1: pdmm0-sdi1 {
> ++ rockchip,pins = <2 RK_PC4 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_sdi2: pdmm0-sdi2 {
> ++ rockchip,pins = <2 RK_PC5 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_sdi3: pdmm0-sdi3 {
> ++ rockchip,pins = <2 RK_PC6 2 &pcfg_pull_none>;
> ++ };
> ++
> ++ pdmm0_clk_sleep: pdmm0-clk-sleep {
> + rockchip,pins =
> +- <0 5 RK_FUNC_1 &pcfg_pull_none>,
> +- <0 6 RK_FUNC_1 &pcfg_pull_none>;
> ++ <2 RK_PC2 RK_FUNC_GPIO
> &pcfg_input_high>;
> + };
> ++
> ++ pdmm0_sdi0_sleep: pdmm0-sdi0-sleep {
> ++ rockchip,pins =
> ++ <2 RK_PC3 RK_FUNC_GPIO
> &pcfg_input_high>;
> ++ };
> ++
> ++ pdmm0_sdi1_sleep: pdmm0-sdi1-sleep {
> ++ rockchip,pins =
> ++ <2 RK_PC4 RK_FUNC_GPIO
> &pcfg_input_high>;
> ++ };
> ++
> ++ pdmm0_sdi2_sleep: pdmm0-sdi2-sleep {
> ++ rockchip,pins =
> ++ <2 RK_PC5 RK_FUNC_GPIO
> &pcfg_input_high>;
> ++ };
> ++
> ++ pdmm0_sdi3_sleep: pdmm0-sdi3-sleep {
> ++ rockchip,pins =
> ++ <2 RK_PC6 RK_FUNC_GPIO
> &pcfg_input_high>;
> ++ };
> ++
> ++ pdmm0_fsync_sleep: pdmm0-fsync-sleep {
> ++ rockchip,pins =
> ++ <2 RK_PC7 RK_FUNC_GPIO
> &pcfg_input_high>;
> ++ };
> + };
> +
> ++ tsadc {
> ++ otp_gpio: otp-gpio {
> ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO
> &pcfg_pull_none>;
> ++ };
> ++
> ++ otp_out: otp-out {
> ++ rockchip,pins = <2 RK_PB5 1 &pcfg_pull_none>;
> ++ };
> ++ };
> ++
> + uart0 {
> + uart0_xfer: uart0-xfer {
> +- rockchip,pins =
> +- <1 9 RK_FUNC_1 &pcfg_pull_up>,
> +- <1 8 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PB1 1 &pcfg_pull_up>,
> ++ <1 RK_PB0 1 &pcfg_pull_none>;
> + };
> +
> + uart0_cts: uart0-cts {
> +- rockchip,pins =
> +- <1 11 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PB3 1 &pcfg_pull_none>;
> + };
> +
> + uart0_rts: uart0-rts {
> +- rockchip,pins =
> +- <1 10 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PB2 1 &pcfg_pull_none>;
> + };
> +
> + uart0_rts_gpio: uart0-rts-gpio {
> +- rockchip,pins =
> +- <1 10 RK_FUNC_GPIO &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PB2 RK_FUNC_GPIO
> &pcfg_pull_none>;
> + };
> + };
> +
> + uart1 {
> + uart1_xfer: uart1-xfer {
> +- rockchip,pins =
> +- <3 4 RK_FUNC_4 &pcfg_pull_up>,
> +- <3 6 RK_FUNC_4 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA4 4 &pcfg_pull_up>,
> ++ <3 RK_PA6 4 &pcfg_pull_none>;
> + };
> +
> + uart1_cts: uart1-cts {
> +- rockchip,pins =
> +- <3 7 RK_FUNC_4 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA7 4 &pcfg_pull_none>;
> + };
> +
> + uart1_rts: uart1-rts {
> +- rockchip,pins =
> +- <3 5 RK_FUNC_4 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA5 4 &pcfg_pull_none>;
> + };
> +
> + uart1_rts_gpio: uart1-rts-gpio {
> +- rockchip,pins =
> +- <3 5 RK_FUNC_GPIO &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA5 RK_FUNC_GPIO
> &pcfg_pull_none>;
> + };
> + };
> +
> + uart2-0 {
> + uart2m0_xfer: uart2m0-xfer {
> +- rockchip,pins =
> +- <1 0 RK_FUNC_2 &pcfg_pull_up>,
> +- <1 1 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PA0 2 &pcfg_pull_up>,
> ++ <1 RK_PA1 2 &pcfg_pull_none>;
> + };
> + };
> +
> + uart2-1 {
> + uart2m1_xfer: uart2m1-xfer {
> +- rockchip,pins =
> +- <2 0 RK_FUNC_1 &pcfg_pull_up>,
> +- <2 1 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA0 1 &pcfg_pull_up>,
> ++ <2 RK_PA1 1 &pcfg_pull_none>;
> + };
> + };
> +
> + spi0-0 {
> + spi0m0_clk: spi0m0-clk {
> +- rockchip,pins =
> +- <2 8 RK_FUNC_1 &pcfg_pull_up>;
> ++ rockchip,pins = <2 RK_PB0 1 &pcfg_pull_up>;
> + };
> +
> + spi0m0_cs0: spi0m0-cs0 {
> +- rockchip,pins =
> +- <2 11 RK_FUNC_1 &pcfg_pull_up>;
> ++ rockchip,pins = <2 RK_PB3 1 &pcfg_pull_up>;
> + };
> +
> + spi0m0_tx: spi0m0-tx {
> +- rockchip,pins =
> +- <2 9 RK_FUNC_1 &pcfg_pull_up>;
> ++ rockchip,pins = <2 RK_PB1 1 &pcfg_pull_up>;
> + };
> +
> + spi0m0_rx: spi0m0-rx {
> +- rockchip,pins =
> +- <2 10 RK_FUNC_1 &pcfg_pull_up>;
> ++ rockchip,pins = <2 RK_PB2 1 &pcfg_pull_up>;
> + };
> +
> + spi0m0_cs1: spi0m0-cs1 {
> +- rockchip,pins =
> +- <2 12 RK_FUNC_1 &pcfg_pull_up>;
> ++ rockchip,pins = <2 RK_PB4 1 &pcfg_pull_up>;
> + };
> + };
> +
> + spi0-1 {
> + spi0m1_clk: spi0m1-clk {
> +- rockchip,pins =
> +- <3 23 RK_FUNC_2 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PC7 2 &pcfg_pull_up>;
> + };
> +
> + spi0m1_cs0: spi0m1-cs0 {
> +- rockchip,pins =
> +- <3 26 RK_FUNC_2 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PD2 2 &pcfg_pull_up>;
> + };
> +
> + spi0m1_tx: spi0m1-tx {
> +- rockchip,pins =
> +- <3 25 RK_FUNC_2 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PD1 2 &pcfg_pull_up>;
> + };
> +
> + spi0m1_rx: spi0m1-rx {
> +- rockchip,pins =
> +- <3 24 RK_FUNC_2 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PD0 2 &pcfg_pull_up>;
> + };
> +
> + spi0m1_cs1: spi0m1-cs1 {
> +- rockchip,pins =
> +- <3 27 RK_FUNC_2 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PD3 2 &pcfg_pull_up>;
> + };
> + };
> +
> + spi0-2 {
> + spi0m2_clk: spi0m2-clk {
> +- rockchip,pins =
> +- <3 0 RK_FUNC_4 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PA0 4 &pcfg_pull_up>;
> + };
> +
> + spi0m2_cs0: spi0m2-cs0 {
> +- rockchip,pins =
> +- <3 8 RK_FUNC_3 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PB0 3 &pcfg_pull_up>;
> + };
> +
> + spi0m2_tx: spi0m2-tx {
> +- rockchip,pins =
> +- <3 1 RK_FUNC_4 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PA1 4 &pcfg_pull_up>;
> + };
> +
> + spi0m2_rx: spi0m2-rx {
> +- rockchip,pins =
> +- <3 2 RK_FUNC_4 &pcfg_pull_up>;
> ++ rockchip,pins = <3 RK_PA2 4 &pcfg_pull_up>;
> + };
> + };
> +
> + i2s1 {
> + i2s1_mclk: i2s1-mclk {
> +- rockchip,pins =
> +- <2 15 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PB7 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sclk: i2s1-sclk {
> +- rockchip,pins =
> +- <2 18 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC2 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_lrckrx: i2s1-lrckrx {
> +- rockchip,pins =
> +- <2 16 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC0 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_lrcktx: i2s1-lrcktx {
> +- rockchip,pins =
> +- <2 17 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC1 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sdi: i2s1-sdi {
> +- rockchip,pins =
> +- <2 19 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC3 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sdo: i2s1-sdo {
> +- rockchip,pins =
> +- <2 23 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC7 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sdio1: i2s1-sdio1 {
> +- rockchip,pins =
> +- <2 20 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC4 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sdio2: i2s1-sdio2 {
> +- rockchip,pins =
> +- <2 21 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC5 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sdio3: i2s1-sdio3 {
> +- rockchip,pins =
> +- <2 22 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC6 1 &pcfg_pull_none>;
> + };
> +
> + i2s1_sleep: i2s1-sleep {
> + rockchip,pins =
> +- <2 15 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 16 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 17 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 18 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 19 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 20 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 21 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 22 RK_FUNC_GPIO &pcfg_input_high>,
> +- <2 23 RK_FUNC_GPIO &pcfg_input_high>;
> ++ <2 RK_PB7 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC0 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC1 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC2 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC3 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC4 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC5 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC6 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <2 RK_PC7 RK_FUNC_GPIO
> &pcfg_input_high>;
> + };
> + };
> +
> + i2s2-0 {
> + i2s2m0_mclk: i2s2m0-mclk {
> +- rockchip,pins =
> +- <1 21 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_sclk: i2s2m0-sclk {
> +- rockchip,pins =
> +- <1 22 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PC6 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_lrckrx: i2s2m0-lrckrx {
> +- rockchip,pins =
> +- <1 26 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PD2 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_lrcktx: i2s2m0-lrcktx {
> +- rockchip,pins =
> +- <1 23 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PC7 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_sdi: i2s2m0-sdi {
> +- rockchip,pins =
> +- <1 24 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PD0 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_sdo: i2s2m0-sdo {
> +- rockchip,pins =
> +- <1 25 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PD1 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m0_sleep: i2s2m0-sleep {
> + rockchip,pins =
> +- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
> +- <1 22 RK_FUNC_GPIO &pcfg_input_high>,
> +- <1 26 RK_FUNC_GPIO &pcfg_input_high>,
> +- <1 23 RK_FUNC_GPIO &pcfg_input_high>,
> +- <1 24 RK_FUNC_GPIO &pcfg_input_high>,
> +- <1 25 RK_FUNC_GPIO &pcfg_input_high>;
> ++ <1 RK_PC5 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <1 RK_PC6 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <1 RK_PD2 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <1 RK_PC7 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <1 RK_PD0 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <1 RK_PD1 RK_FUNC_GPIO
> &pcfg_input_high>;
> + };
> + };
> +
> + i2s2-1 {
> + i2s2m1_mclk: i2s2m1-mclk {
> +- rockchip,pins =
> +- <1 21 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <1 RK_PC5 1 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_sclk: i2s2m1-sclk {
> +- rockchip,pins =
> +- <3 0 RK_FUNC_6 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA0 6 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_lrckrx: i2sm1-lrckrx {
> +- rockchip,pins =
> +- <3 8 RK_FUNC_6 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PB0 6 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_lrcktx: i2s2m1-lrcktx {
> +- rockchip,pins =
> +- <3 8 RK_FUNC_4 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PB0 4 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_sdi: i2s2m1-sdi {
> +- rockchip,pins =
> +- <3 2 RK_FUNC_6 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA2 6 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_sdo: i2s2m1-sdo {
> +- rockchip,pins =
> +- <3 1 RK_FUNC_6 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PA1 6 &pcfg_pull_none>;
> + };
> +
> + i2s2m1_sleep: i2s2m1-sleep {
> + rockchip,pins =
> +- <1 21 RK_FUNC_GPIO &pcfg_input_high>,
> +- <3 0 RK_FUNC_GPIO &pcfg_input_high>,
> +- <3 8 RK_FUNC_GPIO &pcfg_input_high>,
> +- <3 2 RK_FUNC_GPIO &pcfg_input_high>,
> +- <3 1 RK_FUNC_GPIO &pcfg_input_high>;
> ++ <1 RK_PC5 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <3 RK_PA0 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <3 RK_PB0 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <3 RK_PA2 RK_FUNC_GPIO
> &pcfg_input_high>,
> ++ <3 RK_PA1 RK_FUNC_GPIO
> &pcfg_input_high>;
> + };
> + };
> +
> + spdif-0 {
> + spdifm0_tx: spdifm0-tx {
> +- rockchip,pins =
> +- <0 27 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD3 1 &pcfg_pull_none>;
> + };
> + };
> +
> + spdif-1 {
> + spdifm1_tx: spdifm1-tx {
> +- rockchip,pins =
> +- <2 17 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PC1 2 &pcfg_pull_none>;
> + };
> + };
> +
> + spdif-2 {
> + spdifm2_tx: spdifm2-tx {
> +- rockchip,pins =
> +- <0 2 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PA2 2 &pcfg_pull_none>;
> + };
> + };
> +
> + sdmmc0-0 {
> + sdmmc0m0_pwren: sdmmc0m0-pwren {
> +- rockchip,pins =
> +- <2 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <2 RK_PA7 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0m0_gpio: sdmmc0m0-gpio {
> +- rockchip,pins =
> +- <2 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <2 RK_PA7 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>;
> + };
> + };
> +
> + sdmmc0-1 {
> + sdmmc0m1_pwren: sdmmc0m1-pwren {
> +- rockchip,pins =
> +- <0 30 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <0 RK_PD6 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0m1_gpio: sdmmc0m1-gpio {
> +- rockchip,pins =
> +- <0 30 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <0 RK_PD6 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>;
> + };
> + };
> +
> + sdmmc0 {
> + sdmmc0_clk: sdmmc0-clk {
> +- rockchip,pins =
> +- <1 6 RK_FUNC_1 &pcfg_pull_none_4ma>;
> ++ rockchip,pins = <1 RK_PA6 1
> &pcfg_pull_none_4ma>;
> + };
> +
> + sdmmc0_cmd: sdmmc0-cmd {
> +- rockchip,pins =
> +- <1 4 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <1 RK_PA4 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0_dectn: sdmmc0-dectn {
> +- rockchip,pins =
> +- <1 5 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <1 RK_PA5 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0_wrprt: sdmmc0-wrprt {
> +- rockchip,pins =
> +- <1 7 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <1 RK_PA7 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0_bus1: sdmmc0-bus1 {
> +- rockchip,pins =
> +- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0_bus4: sdmmc0-bus4 {
> +- rockchip,pins =
> +- <1 0 RK_FUNC_1 &pcfg_pull_up_4ma>,
> +- <1 1 RK_FUNC_1 &pcfg_pull_up_4ma>,
> +- <1 2 RK_FUNC_1 &pcfg_pull_up_4ma>,
> +- <1 3 RK_FUNC_1 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <1 RK_PA0 1 &pcfg_pull_up_4ma>,
> ++ <1 RK_PA1 1 &pcfg_pull_up_4ma>,
> ++ <1 RK_PA2 1 &pcfg_pull_up_4ma>,
> ++ <1 RK_PA3 1 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0_gpio: sdmmc0-gpio {
> + rockchip,pins =
> +- <1 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
> ++ <1 RK_PA6 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA4 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA5 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA7 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA3 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA2 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA1 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PA0 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>;
> + };
> + };
> +
> + sdmmc0ext {
> + sdmmc0ext_clk: sdmmc0ext-clk {
> +- rockchip,pins =
> +- <3 2 RK_FUNC_3 &pcfg_pull_none_4ma>;
> ++ rockchip,pins = <3 RK_PA2 3
> &pcfg_pull_none_4ma>;
> + };
> +
> + sdmmc0ext_cmd: sdmmc0ext-cmd {
> +- rockchip,pins =
> +- <3 0 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <3 RK_PA0 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0ext_wrprt: sdmmc0ext-wrprt {
> +- rockchip,pins =
> +- <3 3 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <3 RK_PA3 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0ext_dectn: sdmmc0ext-dectn {
> +- rockchip,pins =
> +- <3 1 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <3 RK_PA1 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0ext_bus1: sdmmc0ext-bus1 {
> +- rockchip,pins =
> +- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ rockchip,pins = <3 RK_PA4 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0ext_bus4: sdmmc0ext-bus4 {
> + rockchip,pins =
> +- <3 4 RK_FUNC_3 &pcfg_pull_up_4ma>,
> +- <3 5 RK_FUNC_3 &pcfg_pull_up_4ma>,
> +- <3 6 RK_FUNC_3 &pcfg_pull_up_4ma>,
> +- <3 7 RK_FUNC_3 &pcfg_pull_up_4ma>;
> ++ <3 RK_PA4 3 &pcfg_pull_up_4ma>,
> ++ <3 RK_PA5 3 &pcfg_pull_up_4ma>,
> ++ <3 RK_PA6 3 &pcfg_pull_up_4ma>,
> ++ <3 RK_PA7 3 &pcfg_pull_up_4ma>;
> + };
> +
> + sdmmc0ext_gpio: sdmmc0ext-gpio {
> + rockchip,pins =
> +- <3 0 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 1 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 2 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 3 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 4 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 5 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 6 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <3 7 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
> ++ <3 RK_PA0 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA1 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA2 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA3 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA4 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA5 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA6 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <3 RK_PA7 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>;
> + };
> + };
> +
> + sdmmc1 {
> + sdmmc1_clk: sdmmc1-clk {
> +- rockchip,pins =
> +- <1 12 RK_FUNC_1 &pcfg_pull_none_8ma>;
> ++ rockchip,pins = <1 RK_PB4 1
> &pcfg_pull_none_8ma>;
> + };
> +
> + sdmmc1_cmd: sdmmc1-cmd {
> +- rockchip,pins =
> +- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PB5 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_pwren: sdmmc1-pwren {
> +- rockchip,pins =
> +- <1 18 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PC2 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_wrprt: sdmmc1-wrprt {
> +- rockchip,pins =
> +- <1 20 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PC4 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_dectn: sdmmc1-dectn {
> +- rockchip,pins =
> +- <1 19 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PC3 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_bus1: sdmmc1-bus1 {
> +- rockchip,pins =
> +- <1 14 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_bus4: sdmmc1-bus4 {
> +- rockchip,pins =
> +- <1 12 RK_FUNC_1 &pcfg_pull_up_8ma>,
> +- <1 13 RK_FUNC_1 &pcfg_pull_up_8ma>,
> +- <1 16 RK_FUNC_1 &pcfg_pull_up_8ma>,
> +- <1 17 RK_FUNC_1 &pcfg_pull_up_8ma>;
> ++ rockchip,pins = <1 RK_PB6 1 &pcfg_pull_up_8ma>,
> ++ <1 RK_PB7 1 &pcfg_pull_up_8ma>,
> ++ <1 RK_PC0 1 &pcfg_pull_up_8ma>,
> ++ <1 RK_PC1 1 &pcfg_pull_up_8ma>;
> + };
> +
> + sdmmc1_gpio: sdmmc1-gpio {
> + rockchip,pins =
> +- <1 12 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 13 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 14 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 15 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 16 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 17 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 18 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 19 RK_FUNC_GPIO &pcfg_pull_up_4ma>,
> +- <1 20 RK_FUNC_GPIO &pcfg_pull_up_4ma>;
> ++ <1 RK_PB4 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PB5 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PB6 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PB7 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PC0 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PC1 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PC2 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PC3 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>,
> ++ <1 RK_PC4 RK_FUNC_GPIO
> &pcfg_pull_up_4ma>;
> + };
> + };
> +
> + emmc {
> + emmc_clk: emmc-clk {
> +- rockchip,pins =
> +- <3 21 RK_FUNC_2 &pcfg_pull_none_12ma>;
> ++ rockchip,pins = <3 RK_PC5 2
> &pcfg_pull_none_12ma>;
> + };
> +
> + emmc_cmd: emmc-cmd {
> +- rockchip,pins =
> +- <3 19 RK_FUNC_2 &pcfg_pull_up_12ma>;
> ++ rockchip,pins = <3 RK_PC3 2 &pcfg_pull_up_12ma>;
> + };
> +
> + emmc_pwren: emmc-pwren {
> +- rockchip,pins =
> +- <3 22 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PC6 2 &pcfg_pull_none>;
> + };
> +
> + emmc_rstnout: emmc-rstnout {
> +- rockchip,pins =
> +- <3 20 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <3 RK_PC4 2 &pcfg_pull_none>;
> + };
> +
> + emmc_bus1: emmc-bus1 {
> +- rockchip,pins =
> +- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>;
> ++ rockchip,pins = <0 RK_PA7 2 &pcfg_pull_up_12ma>;
> + };
> +
> + emmc_bus4: emmc-bus4 {
> + rockchip,pins =
> +- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>;
> ++ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD6 2 &pcfg_pull_up_12ma>;
> + };
> +
> + emmc_bus8: emmc-bus8 {
> + rockchip,pins =
> +- <0 7 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 28 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 29 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 30 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <2 31 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <3 16 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <3 17 RK_FUNC_2 &pcfg_pull_up_12ma>,
> +- <3 18 RK_FUNC_2 &pcfg_pull_up_12ma>;
> ++ <0 RK_PA7 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD4 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD5 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD6 2 &pcfg_pull_up_12ma>,
> ++ <2 RK_PD7 2 &pcfg_pull_up_12ma>,
> ++ <3 RK_PC0 2 &pcfg_pull_up_12ma>,
> ++ <3 RK_PC1 2 &pcfg_pull_up_12ma>,
> ++ <3 RK_PC2 2 &pcfg_pull_up_12ma>;
> + };
> + };
> +
> + pwm0 {
> + pwm0_pin: pwm0-pin {
> +- rockchip,pins =
> +- <2 4 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA4 1 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm1 {
> + pwm1_pin: pwm1-pin {
> +- rockchip,pins =
> +- <2 5 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA5 1 &pcfg_pull_none>;
> + };
> + };
> +
> + pwm2 {
> + pwm2_pin: pwm2-pin {
> +- rockchip,pins =
> +- <2 6 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA6 1 &pcfg_pull_none>;
> + };
> + };
> +
> + pwmir {
> + pwmir_pin: pwmir-pin {
> +- rockchip,pins =
> +- <2 2 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PA2 1 &pcfg_pull_none>;
> + };
> + };
> +
> +- gmac-0 {
> +- rgmiim0_pins: rgmiim0-pins {
> +- rockchip,pins =
> +- /* mac_txclk */
> +- <0 8 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_rxclk */
> +- <0 10 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_mdio */
> +- <0 11 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_txen */
> +- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_clk */
> +- <0 24 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxdv */
> +- <0 25 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_mdc */
> +- <0 19 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxd1 */
> +- <0 14 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxd0 */
> +- <0 15 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_txd1 */
> +- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_txd0 */
> +- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_rxd3 */
> +- <0 20 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxd2 */
> +- <0 21 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_txd3 */
> +- <0 23 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_txd2 */
> +- <0 22 RK_FUNC_1 &pcfg_pull_none_12ma>;
> +- };
> +-
> +- rmiim0_pins: rmiim0-pins {
> +- rockchip,pins =
> +- /* mac_mdio */
> +- <0 11 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_txen */
> +- <0 12 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_clk */
> +- <0 24 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxer */
> +- <0 13 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxdv */
> +- <0 25 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_mdc */
> +- <0 19 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxd1 */
> +- <0 14 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_rxd0 */
> +- <0 15 RK_FUNC_1 &pcfg_pull_none>,
> +- /* mac_txd1 */
> +- <0 16 RK_FUNC_1 &pcfg_pull_none_12ma>,
> +- /* mac_txd0 */
> +- <0 17 RK_FUNC_1 &pcfg_pull_none_12ma>;
> +- };
> +- };
> +-
> + gmac-1 {
> + rgmiim1_pins: rgmiim1-pins {
> + rockchip,pins =
> + /* mac_txclk */
> +- <1 12 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PB4 2 &pcfg_pull_none_12ma>,
> + /* mac_rxclk */
> +- <1 13 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB5 2 &pcfg_pull_none_2ma>,
> + /* mac_mdio */
> +- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
> + /* mac_txen */
> +- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PD1 2 &pcfg_pull_none_12ma>,
> + /* mac_clk */
> +- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
> + /* mac_rxdv */
> +- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC6 2 &pcfg_pull_none_2ma>,
> + /* mac_mdc */
> +- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
> + /* mac_rxd1 */
> +- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB2 2 &pcfg_pull_none_2ma>,
> + /* mac_rxd0 */
> +- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB3 2 &pcfg_pull_none_2ma>,
> + /* mac_txd1 */
> +- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PB0 2 &pcfg_pull_none_12ma>,
> + /* mac_txd0 */
> +- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PB1 2 &pcfg_pull_none_12ma>,
> + /* mac_rxd3 */
> +- <1 14 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB6 2 &pcfg_pull_none_2ma>,
> + /* mac_rxd2 */
> +- <1 15 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB7 2 &pcfg_pull_none_2ma>,
> + /* mac_txd3 */
> +- <1 16 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PC0 2 &pcfg_pull_none_12ma>,
> + /* mac_txd2 */
> +- <1 17 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PC1 2 &pcfg_pull_none_12ma>,
> +
> + /* mac_txclk */
> +- <0 8 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PB0 1 &pcfg_pull_none>,
> + /* mac_txen */
> +- <0 12 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PB4 1 &pcfg_pull_none>,
> + /* mac_clk */
> +- <0 24 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PD0 1 &pcfg_pull_none>,
> + /* mac_txd1 */
> +- <0 16 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PC0 1 &pcfg_pull_none>,
> + /* mac_txd0 */
> +- <0 17 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PC1 1 &pcfg_pull_none>,
> + /* mac_txd3 */
> +- <0 23 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PC7 1 &pcfg_pull_none>,
> + /* mac_txd2 */
> +- <0 22 RK_FUNC_1 &pcfg_pull_none>;
> ++ <0 RK_PC6 1 &pcfg_pull_none>;
> + };
> +
> + rmiim1_pins: rmiim1-pins {
> + rockchip,pins =
> + /* mac_mdio */
> +- <1 19 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC3 2 &pcfg_pull_none_2ma>,
> + /* mac_txen */
> +- <1 25 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PD1 2 &pcfg_pull_none_12ma>,
> + /* mac_clk */
> +- <1 21 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC5 2 &pcfg_pull_none_2ma>,
> + /* mac_rxer */
> +- <1 24 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PD0 2 &pcfg_pull_none_2ma>,
> + /* mac_rxdv */
> +- <1 22 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC6 2 &pcfg_pull_none_2ma>,
> + /* mac_mdc */
> +- <1 23 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PC7 2 &pcfg_pull_none_2ma>,
> + /* mac_rxd1 */
> +- <1 10 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB2 2 &pcfg_pull_none_2ma>,
> + /* mac_rxd0 */
> +- <1 11 RK_FUNC_2 &pcfg_pull_none_2ma>,
> ++ <1 RK_PB3 2 &pcfg_pull_none_2ma>,
> + /* mac_txd1 */
> +- <1 8 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PB0 2 &pcfg_pull_none_12ma>,
> + /* mac_txd0 */
> +- <1 9 RK_FUNC_2 &pcfg_pull_none_12ma>,
> ++ <1 RK_PB1 2 &pcfg_pull_none_12ma>,
> +
> + /* mac_mdio */
> +- <0 11 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PB3 1 &pcfg_pull_none>,
> + /* mac_txen */
> +- <0 12 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PB4 1 &pcfg_pull_none>,
> + /* mac_clk */
> +- <0 24 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PD0 1 &pcfg_pull_none>,
> + /* mac_mdc */
> +- <0 19 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PC3 1 &pcfg_pull_none>,
> + /* mac_txd1 */
> +- <0 16 RK_FUNC_1 &pcfg_pull_none>,
> ++ <0 RK_PC0 1 &pcfg_pull_none>,
> + /* mac_txd0 */
> +- <0 17 RK_FUNC_1 &pcfg_pull_none>;
> ++ <0 RK_PC1 1 &pcfg_pull_none>;
> + };
> + };
> +
> + gmac2phy {
> + fephyled_speed100: fephyled-speed100 {
> +- rockchip,pins =
> +- <0 31 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD7 1 &pcfg_pull_none>;
> + };
> +
> + fephyled_speed10: fephyled-speed10 {
> +- rockchip,pins =
> +- <0 30 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD6 1 &pcfg_pull_none>;
> + };
> +
> + fephyled_duplex: fephyled-duplex {
> +- rockchip,pins =
> +- <0 30 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD6 2 &pcfg_pull_none>;
> + };
> +
> + fephyled_rxm0: fephyled-rxm0 {
> +- rockchip,pins =
> +- <0 29 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD5 1 &pcfg_pull_none>;
> + };
> +
> + fephyled_txm0: fephyled-txm0 {
> +- rockchip,pins =
> +- <0 29 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD5 2 &pcfg_pull_none>;
> + };
> +
> + fephyled_linkm0: fephyled-linkm0 {
> +- rockchip,pins =
> +- <0 28 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PD4 1 &pcfg_pull_none>;
> + };
> +
> + fephyled_rxm1: fephyled-rxm1 {
> +- rockchip,pins =
> +- <2 25 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PD1 2 &pcfg_pull_none>;
> + };
> +
> + fephyled_txm1: fephyled-txm1 {
> +- rockchip,pins =
> +- <2 25 RK_FUNC_3 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PD1 3 &pcfg_pull_none>;
> + };
> +
> + fephyled_linkm1: fephyled-linkm1 {
> +- rockchip,pins =
> +- <2 24 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PD0 2 &pcfg_pull_none>;
> + };
> + };
> +
> + tsadc_pin {
> + tsadc_int: tsadc-int {
> +- rockchip,pins =
> +- <2 13 RK_FUNC_2 &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PB5 2 &pcfg_pull_none>;
> + };
> + tsadc_gpio: tsadc-gpio {
> +- rockchip,pins =
> +- <2 13 RK_FUNC_GPIO &pcfg_pull_none>;
> ++ rockchip,pins = <2 RK_PB5 RK_FUNC_GPIO
> &pcfg_pull_none>;
> + };
> + };
> +
> + hdmi_pin {
> + hdmi_cec: hdmi-cec {
> +- rockchip,pins =
> +- <0 3 RK_FUNC_1 &pcfg_pull_none>;
> ++ rockchip,pins = <0 RK_PA3 1 &pcfg_pull_none>;
> + };
> +
> + hdmi_hpd: hdmi-hpd {
> +- rockchip,pins =
> +- <0 4 RK_FUNC_1 &pcfg_pull_down>;
> ++ rockchip,pins = <0 RK_PA4 1 &pcfg_pull_down>;
> + };
> + };
> +
> +@@ -1460,29 +1697,29 @@
> + dvp_d2d9_m0:dvp-d2d9-m0 {
> + rockchip,pins =
> + /* cif_d0 */
> +- <3 4 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA4 2 &pcfg_pull_none>,
> + /* cif_d1 */
> +- <3 5 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA5 2 &pcfg_pull_none>,
> + /* cif_d2 */
> +- <3 6 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA6 2 &pcfg_pull_none>,
> + /* cif_d3 */
> +- <3 7 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA7 2 &pcfg_pull_none>,
> + /* cif_d4 */
> +- <3 8 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PB0 2 &pcfg_pull_none>,
> + /* cif_d5m0 */
> +- <3 9 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PB1 2 &pcfg_pull_none>,
> + /* cif_d6m0 */
> +- <3 10 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PB2 2 &pcfg_pull_none>,
> + /* cif_d7m0 */
> +- <3 11 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PB3 2 &pcfg_pull_none>,
> + /* cif_href */
> +- <3 1 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA1 2 &pcfg_pull_none>,
> + /* cif_vsync */
> +- <3 0 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA0 2 &pcfg_pull_none>,
> + /* cif_clkoutm0 */
> +- <3 3 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA3 2 &pcfg_pull_none>,
> + /* cif_clkin */
> +- <3 2 RK_FUNC_2 &pcfg_pull_none>;
> ++ <3 RK_PA2 2 &pcfg_pull_none>;
> + };
> + };
> +
> +@@ -1490,29 +1727,29 @@
> + dvp_d2d9_m1:dvp-d2d9-m1 {
> + rockchip,pins =
> + /* cif_d0 */
> +- <3 4 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA4 2 &pcfg_pull_none>,
> + /* cif_d1 */
> +- <3 5 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA5 2 &pcfg_pull_none>,
> + /* cif_d2 */
> +- <3 6 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA6 2 &pcfg_pull_none>,
> + /* cif_d3 */
> +- <3 7 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA7 2 &pcfg_pull_none>,
> + /* cif_d4 */
> +- <3 8 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PB0 2 &pcfg_pull_none>,
> + /* cif_d5m1 */
> +- <2 16 RK_FUNC_4 &pcfg_pull_none>,
> ++ <2 RK_PC0 4 &pcfg_pull_none>,
> + /* cif_d6m1 */
> +- <2 17 RK_FUNC_4 &pcfg_pull_none>,
> ++ <2 RK_PC1 4 &pcfg_pull_none>,
> + /* cif_d7m1 */
> +- <2 18 RK_FUNC_4 &pcfg_pull_none>,
> ++ <2 RK_PC2 4 &pcfg_pull_none>,
> + /* cif_href */
> +- <3 1 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA1 2 &pcfg_pull_none>,
> + /* cif_vsync */
> +- <3 0 RK_FUNC_2 &pcfg_pull_none>,
> ++ <3 RK_PA0 2 &pcfg_pull_none>,
> + /* cif_clkoutm1 */
> +- <2 15 RK_FUNC_4 &pcfg_pull_none>,
> ++ <2 RK_PB7 4 &pcfg_pull_none>,
> + /* cif_clkin */
> +- <3 2 RK_FUNC_2 &pcfg_pull_none>;
> ++ <3 RK_PA2 2 &pcfg_pull_none>;
> + };
> + };
> + };
> Index: patches/patch-arch_arm_dts_rk3399-rockpro64_dts
> ===================================================================
> RCS file:
> /cvs/ports/sysutils/u-boot/patches/patch-arch_arm_dts_rk3399-rockpro64_dts,v
> retrieving revision 1.1
> diff -u -p -u -r1.1 patch-arch_arm_dts_rk3399-rockpro64_dts
> --- patches/patch-arch_arm_dts_rk3399-rockpro64_dts 28 Sep 2019 01:40:24
> -0000 1.1
> +++ patches/patch-arch_arm_dts_rk3399-rockpro64_dts 5 Oct 2019 16:15:13
> -0000
> @@ -12,3 +12,52 @@ Index: arch/arm/dts/rk3399-rockpro64.dts
> };
>
> clkin_gmac: external-gmac-clock {
> +@@ -222,6 +222,10 @@
> + status = "okay";
> + };
> +
> ++&hdmi_sound {
> ++ status = "okay";
> ++};
> ++
> + &gpu {
> + mali-supply = <&vdd_gpu>;
> + status = "okay";
> +@@ -504,11 +508,25 @@
> + status = "okay";
> +
> + bt656-supply = <&vcc1v8_dvp>;
> +- audio-supply = <&vcca1v8_codec>;
> ++ audio-supply = <&vcc_3v0>;
> + sdmmc-supply = <&vcc_sdio>;
> + gpio1830-supply = <&vcc_3v0>;
> + };
> +
> ++&pcie0 {
> ++ ep-gpios = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
> ++ num-lanes = <4>;
> ++ pinctrl-names = "default";
> ++ pinctrl-0 = <&pcie_perst>;
> ++ vpcie12v-supply = <&vcc12v_dcin>;
> ++ vpcie3v3-supply = <&vcc3v3_pcie>;
> ++ status = "okay";
> ++};
> ++
> ++&pcie_phy {
> ++ status = "okay";
> ++};
> ++
> + &pmu_io_domains {
> + pmu1830-supply = <&vcc_3v0>;
> + status = "okay";
> +@@ -538,6 +556,10 @@
> + };
> +
> + pcie {
> ++ pcie_perst: pcie-perst {
> ++ rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
> ++ };
> ++
> + pcie_pwr_en: pcie-pwr-en {
> + rockchip,pins = <1 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
> + };
> Index: patches/patch-configs_rock64-rk3328_defconfig
> ===================================================================
> RCS file: patches/patch-configs_rock64-rk3328_defconfig
> diff -N patches/patch-configs_rock64-rk3328_defconfig
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-configs_rock64-rk3328_defconfig 5 Oct 2019 16:15:13
> -0000
> @@ -0,0 +1,14 @@
> +$OpenBSD$
> +
> +Index: configs/rock64-rk3328_defconfig
> +--- configs/rock64-rk3328_defconfig.orig
> ++++ configs/rock64-rk3328_defconfig
> +@@ -76,7 +76,7 @@ CONFIG_RAM=y
> + CONFIG_SPL_RAM=y
> + CONFIG_TPL_RAM=y
> + CONFIG_DM_RESET=y
> +-CONFIG_BAUDRATE=1500000
> ++CONFIG_BAUDRATE=115200
> + CONFIG_DEBUG_UART_SHIFT=2
> + CONFIG_SYSRESET=y
> + CONFIG_USB=y
> Index: patches/patch-include_dt-bindings_clock_rk3328-cru_h
> ===================================================================
> RCS file: patches/patch-include_dt-bindings_clock_rk3328-cru_h
> diff -N patches/patch-include_dt-bindings_clock_rk3328-cru_h
> --- /dev/null 1 Jan 1970 00:00:00 -0000
> +++ patches/patch-include_dt-bindings_clock_rk3328-cru_h 5 Oct 2019
> 16:15:13 -0000
> @@ -0,0 +1,237 @@
> +$OpenBSD$
> +
> +Index: include/dt-bindings/clock/rk3328-cru.h
> +--- include/dt-bindings/clock/rk3328-cru.h.orig
> ++++ include/dt-bindings/clock/rk3328-cru.h
> +@@ -1,6 +1,7 @@
> +-/* SPDX-License-Identifier: GPL-2.0+ */
> ++/* SPDX-License-Identifier: GPL-2.0-or-later */
> + /*
> +- * (C) Copyright 2016 Rockchip Electronics Co., Ltd
> ++ * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
> ++ * Author: Elaine <zhangq...@rock-chips.com>
> + */
> +
> + #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RK3328_H
> +@@ -90,118 +91,117 @@
> + #define SCLK_MAC2IO_EXT 102
> +
> + /* dclk gates */
> +-#define DCLK_LCDC 180
> +-#define DCLK_HDMIPHY 181
> +-#define HDMIPHY 182
> +-#define USB480M 183
> +-#define DCLK_LCDC_SRC 184
> ++#define DCLK_LCDC 120
> ++#define DCLK_HDMIPHY 121
> ++#define HDMIPHY 122
> ++#define USB480M 123
> ++#define DCLK_LCDC_SRC 124
> +
> + /* aclk gates */
> +-#define ACLK_AXISRAM 190
> +-#define ACLK_VOP_PRE 191
> +-#define ACLK_USB3OTG 192
> +-#define ACLK_RGA_PRE 193
> +-#define ACLK_DMAC 194
> +-#define ACLK_GPU 195
> +-#define ACLK_BUS_PRE 196
> +-#define ACLK_PERI_PRE 197
> +-#define ACLK_RKVDEC_PRE 198
> +-#define ACLK_RKVDEC 199
> +-#define ACLK_RKVENC 200
> +-#define ACLK_VPU_PRE 201
> +-#define ACLK_VIO_PRE 202
> +-#define ACLK_VPU 203
> +-#define ACLK_VIO 204
> +-#define ACLK_VOP 205
> +-#define ACLK_GMAC 206
> +-#define ACLK_H265 207
> +-#define ACLK_H264 208
> +-#define ACLK_MAC2PHY 209
> +-#define ACLK_MAC2IO 210
> +-#define ACLK_DCF 211
> +-#define ACLK_TSP 212
> +-#define ACLK_PERI 213
> +-#define ACLK_RGA 214
> +-#define ACLK_IEP 215
> +-#define ACLK_CIF 216
> +-#define ACLK_HDCP 217
> ++#define ACLK_AXISRAM 130
> ++#define ACLK_VOP_PRE 131
> ++#define ACLK_USB3OTG 132
> ++#define ACLK_RGA_PRE 133
> ++#define ACLK_DMAC 134
> ++#define ACLK_GPU 135
> ++#define ACLK_BUS_PRE 136
> ++#define ACLK_PERI_PRE 137
> ++#define ACLK_RKVDEC_PRE 138
> ++#define ACLK_RKVDEC 139
> ++#define ACLK_RKVENC 140
> ++#define ACLK_VPU_PRE 141
> ++#define ACLK_VIO_PRE 142
> ++#define ACLK_VPU 143
> ++#define ACLK_VIO 144
> ++#define ACLK_VOP 145
> ++#define ACLK_GMAC 146
> ++#define ACLK_H265 147
> ++#define ACLK_H264 148
> ++#define ACLK_MAC2PHY 149
> ++#define ACLK_MAC2IO 150
> ++#define ACLK_DCF 151
> ++#define ACLK_TSP 152
> ++#define ACLK_PERI 153
> ++#define ACLK_RGA 154
> ++#define ACLK_IEP 155
> ++#define ACLK_CIF 156
> ++#define ACLK_HDCP 157
> +
> + /* pclk gates */
> +-#define PCLK_GPIO0 300
> +-#define PCLK_GPIO1 301
> +-#define PCLK_GPIO2 302
> +-#define PCLK_GPIO3 303
> +-#define PCLK_GRF 304
> +-#define PCLK_I2C0 305
> +-#define PCLK_I2C1 306
> +-#define PCLK_I2C2 307
> +-#define PCLK_I2C3 308
> +-#define PCLK_SPI 309
> +-#define PCLK_UART0 310
> +-#define PCLK_UART1 311
> +-#define PCLK_UART2 312
> +-#define PCLK_TSADC 313
> +-#define PCLK_PWM 314
> +-#define PCLK_TIMER 315
> +-#define PCLK_BUS_PRE 316
> +-#define PCLK_PERI_PRE 317
> +-#define PCLK_HDMI_CTRL 318
> +-#define PCLK_HDMI_PHY 319
> +-#define PCLK_GMAC 320
> +-#define PCLK_H265 321
> +-#define PCLK_MAC2PHY 322
> +-#define PCLK_MAC2IO 323
> +-#define PCLK_USB3PHY_OTG 324
> +-#define PCLK_USB3PHY_PIPE 325
> +-#define PCLK_USB3_GRF 326
> +-#define PCLK_USB2_GRF 327
> +-#define PCLK_HDMIPHY 328
> +-#define PCLK_DDR 329
> +-#define PCLK_PERI 330
> +-#define PCLK_HDMI 331
> +-#define PCLK_HDCP 332
> +-#define PCLK_DCF 333
> +-#define PCLK_SARADC 334
> ++#define PCLK_GPIO0 200
> ++#define PCLK_GPIO1 201
> ++#define PCLK_GPIO2 202
> ++#define PCLK_GPIO3 203
> ++#define PCLK_GRF 204
> ++#define PCLK_I2C0 205
> ++#define PCLK_I2C1 206
> ++#define PCLK_I2C2 207
> ++#define PCLK_I2C3 208
> ++#define PCLK_SPI 209
> ++#define PCLK_UART0 210
> ++#define PCLK_UART1 211
> ++#define PCLK_UART2 212
> ++#define PCLK_TSADC 213
> ++#define PCLK_PWM 214
> ++#define PCLK_TIMER 215
> ++#define PCLK_BUS_PRE 216
> ++#define PCLK_PERI_PRE 217
> ++#define PCLK_HDMI_CTRL 218
> ++#define PCLK_HDMI_PHY 219
> ++#define PCLK_GMAC 220
> ++#define PCLK_H265 221
> ++#define PCLK_MAC2PHY 222
> ++#define PCLK_MAC2IO 223
> ++#define PCLK_USB3PHY_OTG 224
> ++#define PCLK_USB3PHY_PIPE 225
> ++#define PCLK_USB3_GRF 226
> ++#define PCLK_USB2_GRF 227
> ++#define PCLK_HDMIPHY 228
> ++#define PCLK_DDR 229
> ++#define PCLK_PERI 230
> ++#define PCLK_HDMI 231
> ++#define PCLK_HDCP 232
> ++#define PCLK_DCF 233
> ++#define PCLK_SARADC 234
> ++#define PCLK_ACODECPHY 235
> ++#define PCLK_WDT 236
> +
> + /* hclk gates */
> +-#define HCLK_PERI 408
> +-#define HCLK_TSP 409
> +-#define HCLK_GMAC 410
> +-#define HCLK_I2S0_8CH 411
> +-#define HCLK_I2S1_8CH 413
> +-#define HCLK_I2S2_2CH 413
> +-#define HCLK_SPDIF_8CH 414
> +-#define HCLK_VOP 415
> +-#define HCLK_NANDC 416
> +-#define HCLK_SDMMC 417
> +-#define HCLK_SDIO 418
> +-#define HCLK_EMMC 419
> +-#define HCLK_SDMMC_EXT 420
> +-#define HCLK_RKVDEC_PRE 421
> +-#define HCLK_RKVDEC 422
> +-#define HCLK_RKVENC 423
> +-#define HCLK_VPU_PRE 424
> +-#define HCLK_VIO_PRE 425
> +-#define HCLK_VPU 426
> +-#define HCLK_VIO 427
> +-#define HCLK_BUS_PRE 428
> +-#define HCLK_PERI_PRE 429
> +-#define HCLK_H264 430
> +-#define HCLK_CIF 431
> +-#define HCLK_OTG_PMU 432
> +-#define HCLK_OTG 433
> +-#define HCLK_HOST0 434
> +-#define HCLK_HOST0_ARB 435
> +-#define HCLK_CRYPTO_MST 436
> +-#define HCLK_CRYPTO_SLV 437
> +-#define HCLK_PDM 438
> +-#define HCLK_IEP 439
> +-#define HCLK_RGA 440
> +-#define HCLK_HDCP 441
> ++#define HCLK_PERI 308
> ++#define HCLK_TSP 309
> ++#define HCLK_GMAC 310
> ++#define HCLK_I2S0_8CH 311
> ++#define HCLK_I2S1_8CH 312
> ++#define HCLK_I2S2_2CH 313
> ++#define HCLK_SPDIF_8CH 314
> ++#define HCLK_VOP 315
> ++#define HCLK_NANDC 316
> ++#define HCLK_SDMMC 317
> ++#define HCLK_SDIO 318
> ++#define HCLK_EMMC 319
> ++#define HCLK_SDMMC_EXT 320
> ++#define HCLK_RKVDEC_PRE 321
> ++#define HCLK_RKVDEC 322
> ++#define HCLK_RKVENC 323
> ++#define HCLK_VPU_PRE 324
> ++#define HCLK_VIO_PRE 325
> ++#define HCLK_VPU 326
> ++#define HCLK_BUS_PRE 328
> ++#define HCLK_PERI_PRE 329
> ++#define HCLK_H264 330
> ++#define HCLK_CIF 331
> ++#define HCLK_OTG_PMU 332
> ++#define HCLK_OTG 333
> ++#define HCLK_HOST0 334
> ++#define HCLK_HOST0_ARB 335
> ++#define HCLK_CRYPTO_MST 336
> ++#define HCLK_CRYPTO_SLV 337
> ++#define HCLK_PDM 338
> ++#define HCLK_IEP 339
> ++#define HCLK_RGA 340
> ++#define HCLK_HDCP 341
> +
> + #define CLK_NR_CLKS (HCLK_HDCP + 1)
> +-
> +-#define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1)
> +
> + /* soft-reset indices */
> + #define SRST_CORE0_PO 0
> Index: pkg/PFRAG.aarch64
> ===================================================================
> RCS file: /cvs/ports/sysutils/u-boot/pkg/PFRAG.aarch64,v
> retrieving revision 1.13
> diff -u -p -u -r1.13 PFRAG.aarch64
> --- pkg/PFRAG.aarch64 28 Sep 2019 01:40:25 -0000 1.13
> +++ pkg/PFRAG.aarch64 5 Oct 2019 16:15:13 -0000
> @@ -1,5 +1,13 @@
> @comment $OpenBSD: PFRAG.aarch64,v 1.13 2019/09/28 01:40:25 jsg Exp $
> @pkgpath sysutils/u-boot-pinebook
> +libexec/u-boot/
> +libexec/u-boot/firefly-rk3399/
> +@bin libexec/u-boot/firefly-rk3399/mkimage
> +libexec/u-boot/mkidbloader-rkbin
> +libexec/u-boot/rock64-rk3328/
> +@bin libexec/u-boot/rock64-rk3328/mkimage
> +libexec/u-boot/rockpro64-rk3399/
> +@bin libexec/u-boot/rockpro64-rk3399/mkimage
> share/u-boot/
> share/u-boot/a64-olinuxino/
> share/u-boot/a64-olinuxino/sunxi-spl.bin
> @@ -18,6 +26,7 @@ share/u-boot/bananapi_m64/u-boot.itb
> share/u-boot/firefly-rk3399/
> share/u-boot/firefly-rk3399/idbloader.img
> share/u-boot/firefly-rk3399/u-boot
> +share/u-boot/firefly-rk3399/u-boot-spl-dtb.bin
> share/u-boot/firefly-rk3399/u-boot.bin
> share/u-boot/firefly-rk3399/u-boot.img
> share/u-boot/firefly-rk3399/u-boot.itb
> @@ -86,9 +95,16 @@ share/u-boot/pinebook/u-boot.itb
> share/u-boot/qemu_arm64/
> share/u-boot/qemu_arm64/u-boot
> share/u-boot/qemu_arm64/u-boot.bin
> +share/u-boot/rock64-rk3328/
> +share/u-boot/rock64-rk3328/u-boot
> +share/u-boot/rock64-rk3328/u-boot-spl-dtb.bin
> +share/u-boot/rock64-rk3328/u-boot.bin
> +share/u-boot/rock64-rk3328/u-boot.img
> +share/u-boot/rock64-rk3328/u-boot.itb
> share/u-boot/rockpro64-rk3399/
> share/u-boot/rockpro64-rk3399/idbloader.img
> share/u-boot/rockpro64-rk3399/u-boot
> +share/u-boot/rockpro64-rk3399/u-boot-spl-dtb.bin
> share/u-boot/rockpro64-rk3399/u-boot.bin
> share/u-boot/rockpro64-rk3399/u-boot.img
> share/u-boot/rockpro64-rk3399/u-boot.itb
> Index: pkg/PFRAG.arm
> ===================================================================
> RCS file: /cvs/ports/sysutils/u-boot/pkg/PFRAG.arm,v
> retrieving revision 1.20
> diff -u -p -u -r1.20 PFRAG.arm
> --- pkg/PFRAG.arm 28 Sep 2019 01:40:25 -0000 1.20
> +++ pkg/PFRAG.arm 5 Oct 2019 16:15:13 -0000
> @@ -146,6 +146,7 @@ share/u-boot/bananapi_m2_zero/u-boot.bin
> share/u-boot/bananapi_m2_zero/u-boot.img
> share/u-boot/clearfog/
> share/u-boot/clearfog/u-boot
> +share/u-boot/clearfog/u-boot-spl-dtb.bin
> share/u-boot/clearfog/u-boot-spl.kwb
> share/u-boot/clearfog/u-boot.bin
> share/u-boot/clearfog/u-boot.img
> @@ -243,10 +244,12 @@ share/u-boot/rpi_3_32b/u-boot.bin
> share/u-boot/tinker-rk3288/
> share/u-boot/tinker-rk3288/idbloader.img
> share/u-boot/tinker-rk3288/u-boot
> +share/u-boot/tinker-rk3288/u-boot-spl-dtb.bin
> share/u-boot/tinker-rk3288/u-boot.bin
> share/u-boot/tinker-rk3288/u-boot.img
> share/u-boot/turris_omnia/
> share/u-boot/turris_omnia/u-boot
> +share/u-boot/turris_omnia/u-boot-spl-dtb.bin
> share/u-boot/turris_omnia/u-boot-spl.kwb
> share/u-boot/turris_omnia/u-boot.bin
> share/u-boot/turris_omnia/u-boot.img
>
