Hi,
I've got an issue with a ROCK64 : only one USB port is working, the two
other aren't.
Nothing appears in dmesg when I plus a drive.
The drive does'nt seem powered.

Here is the dmesg : 

        OpenBSD 6.4 (GENERIC.MP) #3: Thu Dec 20 18:14:10 CET 2018
                
r...@syspatch-64-arm64.openbsd.org:/usr/src/sys/arch/arm64/compile/GENERIC.MP
        real mem  = 4213940224 (4018MB)
        avail mem = 4050907136 (3863MB)
        mainbus0 at root: Pine64 Rock64
        cpu0 at mainbus0 mpidr 0: ARM Cortex-A53 r0p4
        cpu0: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 
D-cache
        cpu0: 256KB 64b/line 16-way L2 cache
        efi0 at mainbus0: UEFI 2.0.5
        efi0: Das U-boot rev 0x0
        psci0 at mainbus0: PSCI 1.0
        syscon0 at mainbus0: "syscon"
        rkclock0 at mainbus0
        syscon1 at mainbus0: "syscon"
        ampintc0 at mainbus0 nirq 160, ncpu 4 ipi: 0, 1: "interrupt-controller"
        rkpinctrl0 at mainbus0: "pinctrl"
        rkgpio0 at rkpinctrl0
        rkgpio1 at rkpinctrl0
        rkgpio2 at rkpinctrl0
        rkgpio3 at rkpinctrl0
        simplebus0 at mainbus0: "amba"
        agtimer0 at mainbus0: tick rate 24000 KHz
        com0 at mainbus0: ns16550, no working fifo
        com0: console
        rkiic0 at mainbus0
        iic0 at rkiic0
        rkpmic0 at iic0 addr 0x18: RK805
        rktemp0 at mainbus0
        dwmmc0 at mainbus0: 48 MHz base clock
        sdmmc0 at dwmmc0: 4-bit, sd high-speed, mmc high-speed, dma
        dwmmc1 at mainbus0: 48 MHz base clock
        sdmmc1 at dwmmc1: 8-bit, mmc high-speed, dma
        dwge0 at mainbus0
        dwge0: address: d6:8f:58:d2:50:ce
        rgephy0 at dwge0 phy 0: RTL8169S/8110S/8211 PHY, rev. 6
        ehci0 at mainbus0
        usb0 at ehci0: USB revision 2.0
        uhub0 at usb0 configuration 1 interface 0 "Generic EHCI root hub" rev 
2.00/1.00 addr 1
        cpu1 at mainbus0 mpidr 1: ARM Cortex-A53 r0p4
        cpu1: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 
D-cache
        cpu1: 256KB 64b/line 16-way L2 cache
        cpu2 at mainbus0 mpidr 2: ARM Cortex-A53 r0p4
        cpu2: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 
D-cache
        cpu2: 256KB 64b/line 16-way L2 cache
        cpu3 at mainbus0 mpidr 3: ARM Cortex-A53 r0p4
        cpu3: 32KB 64b/line 2-way L1 VIPT I-cache, 32KB 64b/line 4-way L1 
D-cache
        cpu3: 256KB 64b/line 16-way L2 cache
        scsibus0 at sdmmc1: 2 targets, initiator 0
        sd0 at scsibus0 targ 1 lun 0: <SD/MMC, NCard, 0000> SCSI2 0/direct 
removable
        sd0: 29600MB, 512 bytes/sector, 60620800 sectors
        scsibus1 at sdmmc0: 2 targets, initiator 0
        sd1 at scsibus1 targ 1 lun 0: <SD/MMC, USD00, 0010> SCSI2 0/direct 
removable
        sd1: 15080MB, 512 bytes/sector, 30883840 sectors
        umass0 at uhub0 port 1 configuration 1 interface 0 "Western Digital Ext 
HDD 1021" rev 2.00/20.21 addr 2
        umass0: using SCSI over Bulk-Only
        scsibus2 at umass0: 2 targets, initiator 0
        sd2 at scsibus2 targ 1 lun 0: <WD, Ext HDD 1021, 2021> SCSI2 0/direct 
fixed serial.10581021383235373034
        sd2: 1907727MB, 512 bytes/sector, 3907024896 sectors
        vscsi0 at root
        scsibus3 at vscsi0: 256 targets
        softraid0 at root
        scsibus4 at softraid0: 256 targets
        bootfile: sd0a:/bsd
        boot device: sd0
        root on sd0a (532ea4ce9a5e001c.a) swap on sd0b dump on sd0b
        rk3328_set_frequency: 0x00000006
        cpu0: clock not implemented

-- 
    thuban

Reply via email to