Yes it seems the ALE changes from NetBSD don't help.
Here is an updated version of the diff from
http://marc.info/?l=openbsd-tech&m=139731502408655&w=2
Index: if_cpsw.c
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpsw.c,v
retrieving revision 1.23
diff -u -p -r1.23 if_cpsw.c
--- if_cpsw.c 18 Aug 2014 17:56:45 -0000 1.23
+++ if_cpsw.c 6 Nov 2014 10:32:07 -0000
@@ -128,7 +128,7 @@ struct cpsw_softc {
struct arpcom sc_ac;
struct mii_data sc_mii;
-
+ bool sc_phy_has_1000t;
struct cpsw_ring_data *sc_rdp;
volatile u_int sc_txnext;
volatile u_int sc_txhead;
@@ -175,7 +175,22 @@ int cpsw_rxintr(void *);
int cpsw_txintr(void *);
int cpsw_miscintr(void *);
+#define CPSW_MAX_ALE_ENTRIES 1024
+
+int cpsw_ale_update_addresses(struct cpsw_softc *, int);
+void cpsw_ale_entry_init(uint32_t *);
+void cpsw_ale_entry_set_mac(uint32_t *, const uint8_t *);
+void cpsw_ale_entry_set_bcast_mac(uint32_t *);
+void cpsw_ale_entry_set(uint32_t *, ale_entry_filed_t, uint32_t);
+bool cpsw_ale_entry_mac_match(const uint32_t *, const uint8_t *);
+void cpsw_ale_set_outgoing_mac(struct cpsw_softc *, int, const uint8_t *);
+void cpsw_ale_read_entry(struct cpsw_softc *, uint16_t, uint32_t *);
+void cpsw_ale_write_entry(struct cpsw_softc *, uint16_t, uint32_t *);
+int cpsw_ale_remove_all_mc_entries(struct cpsw_softc *);
+int cpsw_ale_mc_entry_set(struct cpsw_softc *, uint8_t, uint8_t *);
+int cpsw_ale_update_addresses(struct cpsw_softc *, int);
void cpsw_get_mac_addr(struct cpsw_softc *);
+bool cpsw_phy_has_1000t(struct cpsw_softc * const);
struct cfattach cpsw_ca = {
sizeof(struct cpsw_softc),
@@ -286,6 +301,18 @@ cpsw_get_mac_addr(struct cpsw_softc *sc)
}
}
+bool
+cpsw_phy_has_1000t(struct cpsw_softc * const sc)
+{
+ struct ifmedia_entry *ifm;
+
+ TAILQ_FOREACH(ifm, &sc->sc_mii.mii_media.ifm_list, ifm_list) {
+ if (IFM_SUBTYPE(ifm->ifm_media) == IFM_1000_T)
+ return true;
+ }
+ return false;
+}
+
void
cpsw_attach(struct device *parent, struct device *self, void *aux)
{
@@ -393,14 +420,32 @@ cpsw_attach(struct device *parent, struc
ifmedia_init(&sc->sc_mii.mii_media, 0, cpsw_mediachange,
cpsw_mediastatus);
+
+ /* Initialize MDIO */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, MDIOCONTROL,
+ MDIOCTL_ENABLE | MDIOCTL_FAULTENB | MDIOCTL_CLKDIV(0xff));
+ /* Clear ALE */
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_CONTROL,
+ ALECTL_CLEAR_TABLE);
+
mii_attach(self, &sc->sc_mii, 0xffffffff,
MII_PHY_ANY, MII_OFFSET_ANY, 0);
if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) {
printf("no PHY found!\n");
+ sc->sc_phy_has_1000t = false;
ifmedia_add(&sc->sc_mii.mii_media,
IFM_ETHER|IFM_MANUAL, 0, NULL);
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_MANUAL);
} else {
+ sc->sc_phy_has_1000t = cpsw_phy_has_1000t(sc);
+ if (sc->sc_phy_has_1000t) {
+ printf("1000baseT PHY found. setting RGMII Mode\n");
+ /* Select Interface RGMII Mode in the Control Module */
+ sitara_cm_reg_write_4(CPSW_GMII_SEL,
+ GMIISEL_GMII2_SEL(RGMII_MODE) |
+ GMIISEL_GMII1_SEL(RGMII_MODE));
+ }
+
ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO);
}
@@ -769,6 +814,8 @@ cpsw_init(struct ifnet *ifp)
/* Reset and init Sliver port 1 and 2 */
for (i = 0; i < 2; i++) {
+ uint32_t macctl;
+
/* Reset */
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
CPSW_SL_SOFT_RESET(i), 1);
while(bus_space_read_4(sc->sc_bst, sc->sc_bsh,
CPSW_SL_SOFT_RESET(i)) & 1);
@@ -783,10 +830,13 @@ cpsw_init(struct ifnet *ifp)
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
CPSW_PORT_P_SA_LO(i+1),
ac->ac_enaddr[4] | (ac->ac_enaddr[5] << 8));
- /* Set MACCONTROL for ports 0,1: FULLDUPLEX(1), GMII_EN(5),
- IFCTL_A(15), IFCTL_B(16) FIXME */
+ /* Set MACCONTROL for ports 0,1 */
+ macctl = SLMACCTL_FULLDUPLEX | SLMACCTL_GMII_EN |
+ SLMACCTL_IFCTL_A;
+ if (sc->sc_phy_has_1000t)
+ macctl |= SLMACCTL_GIG;
bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SL_MACCONTROL(i),
- 1 | (1<<5) | (1<<15) | (1<<16));
+ macctl);
/* Set ALE port to forwarding(3) */
bus_space_write_4(sc->sc_bst, sc->sc_bsh,
CPSW_ALE_PORTCTL(i+1), 3);
@@ -799,6 +849,9 @@ cpsw_init(struct ifnet *ifp)
/* Set ALE port to forwarding(3) */
bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_PORTCTL(0), 3);
+ /* Initialize addrs */
+ cpsw_ale_update_addresses(sc, 1);
+
bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_PTYPE, 0);
bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_SS_STAT_PORT_EN, 7);
@@ -1207,4 +1260,195 @@ cpsw_miscintr(void *arg)
bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_CPDMA_CPDMA_EOI_VECTOR,
CPSW_INTROFF_MISC);
return 1;
+}
+/*
+ * ALE support routines.
+ */
+
+void
+cpsw_ale_entry_init(uint32_t *ale_entry)
+{
+ ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
+}
+
+void
+cpsw_ale_entry_set_mac(uint32_t *ale_entry, const uint8_t *mac)
+{
+ ale_entry[0] = mac[2] << 24 | mac[3] << 16 | mac[4] << 8 | mac[5];
+ ale_entry[1] = mac[0] << 8 | mac[1];
+}
+
+void
+cpsw_ale_entry_set_bcast_mac(uint32_t *ale_entry)
+{
+ ale_entry[0] = 0xffffffff;
+ ale_entry[1] = 0x0000ffff;
+}
+
+void
+cpsw_ale_entry_set(uint32_t *ale_entry, ale_entry_filed_t field, uint32_t val)
+{
+ /* Entry type[61:60] is addr entry(1), Mcast fwd state[63:62] is fw(3)*/
+ switch (field) {
+ case ALE_ENTRY_TYPE:
+ /* [61:60] */
+ ale_entry[1] |= (val & 0x3) << 28;
+ break;
+ case ALE_MCAST_FWD_STATE:
+ /* [63:62] */
+ ale_entry[1] |= (val & 0x3) << 30;
+ break;
+ case ALE_PORT_MASK:
+ /* [68:66] */
+ ale_entry[2] |= (val & 0x7) << 2;
+ break;
+ case ALE_PORT_NUMBER:
+ /* [67:66] */
+ ale_entry[2] |= (val & 0x3) << 2;
+ break;
+ default:
+ panic("Invalid ALE entry field: %d\n", field);
+ }
+
+ return;
+}
+
+bool
+cpsw_ale_entry_mac_match(const uint32_t *ale_entry, const uint8_t *mac)
+{
+ return (((ale_entry[1] >> 8) & 0xff) == mac[0]) &&
+ (((ale_entry[1] >> 0) & 0xff) == mac[1]) &&
+ (((ale_entry[0] >>24) & 0xff) == mac[2]) &&
+ (((ale_entry[0] >>16) & 0xff) == mac[3]) &&
+ (((ale_entry[0] >> 8) & 0xff) == mac[4]) &&
+ (((ale_entry[0] >> 0) & 0xff) == mac[5]);
+}
+
+void
+cpsw_ale_set_outgoing_mac(struct cpsw_softc *sc, int port, const uint8_t *mac)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P_SA_HI(port),
+ mac[3] << 24 | mac[2] << 16 | mac[1] << 8 | mac[0]);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_PORT_P_SA_LO(port),
+ mac[5] << 8 | mac[4]);
+}
+
+void
+cpsw_ale_read_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLCTL, idx & 1023);
+ ale_entry[0] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW0);
+ ale_entry[1] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW1);
+ ale_entry[2] = bus_space_read_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW2);
+}
+
+void
+cpsw_ale_write_entry(struct cpsw_softc *sc, uint16_t idx, uint32_t *ale_entry)
+{
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW0, ale_entry[0]);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW1, ale_entry[1]);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLW2, ale_entry[2]);
+ bus_space_write_4(sc->sc_bst, sc->sc_bsh, CPSW_ALE_TBLCTL,
+ 1 << 31 | (idx & 1023));
+}
+
+int
+cpsw_ale_remove_all_mc_entries(struct cpsw_softc *sc)
+{
+ int i;
+ uint32_t ale_entry[3];
+
+ /* First two entries are link address and broadcast. */
+ for (i = 2; i < CPSW_MAX_ALE_ENTRIES; i++) {
+ cpsw_ale_read_entry(sc, i, ale_entry);
+ if (((ale_entry[1] >> 28) & 3) == 1 && /* Address entry */
+ ((ale_entry[1] >> 8) & 1) == 1) { /* MCast link addr */
+ ale_entry[0] = ale_entry[1] = ale_entry[2] = 0;
+ cpsw_ale_write_entry(sc, i, ale_entry);
+ }
+ }
+ return CPSW_MAX_ALE_ENTRIES;
+}
+
+int
+cpsw_ale_mc_entry_set(struct cpsw_softc *sc, uint8_t portmask, uint8_t *mac)
+{
+ int free_index = -1, matching_index = -1, i;
+ uint32_t ale_entry[3];
+
+ /* Find a matching entry or a free entry. */
+ for (i = 0; i < CPSW_MAX_ALE_ENTRIES; i++) {
+ cpsw_ale_read_entry(sc, i, ale_entry);
+
+ /* Entry Type[61:60] is 0 for free entry */
+ if (free_index < 0 && ((ale_entry[1] >> 28) & 3) == 0) {
+ free_index = i;
+ }
+
+ if (cpsw_ale_entry_mac_match(ale_entry, mac)) {
+ matching_index = i;
+ break;
+ }
+ }
+
+ if (matching_index < 0) {
+ if (free_index < 0)
+ return ENOMEM;
+ i = free_index;
+ }
+
+ cpsw_ale_entry_init(ale_entry);
+
+ cpsw_ale_entry_set_mac(ale_entry, mac);
+ cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS);
+ cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY);
+ cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, portmask);
+
+ cpsw_ale_write_entry(sc, i, ale_entry);
+
+ return 0;
+}
+
+int
+cpsw_ale_update_addresses(struct cpsw_softc *sc, int purge)
+{
+ struct arpcom *ac = &sc->sc_ac;
+ uint8_t *mac = ac->ac_enaddr;
+ uint32_t ale_entry[3];
+ int i;
+ struct ether_multi *ifma;
+
+ cpsw_ale_entry_init(ale_entry);
+ /* Route incoming packets for our MAC address to Port 0 (host). */
+ /* For simplicity, keep this entry at table index 0 in the ALE. */
+ cpsw_ale_entry_set_mac(ale_entry, mac);
+ cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS);
+ cpsw_ale_entry_set(ale_entry, ALE_PORT_NUMBER, 0);
+ cpsw_ale_write_entry(sc, 0, ale_entry);
+
+ /* Set outgoing MAC Address for Ports 1 and 2. */
+ for (i = 1; i < 3; ++i)
+ cpsw_ale_set_outgoing_mac(sc, i, mac);
+
+ /* Keep the broadcast address at table entry 1. */
+ cpsw_ale_entry_init(ale_entry);
+ cpsw_ale_entry_set_bcast_mac(ale_entry);
+ cpsw_ale_entry_set(ale_entry, ALE_ENTRY_TYPE, ALE_TYPE_ADDRESS);
+ cpsw_ale_entry_set(ale_entry, ALE_MCAST_FWD_STATE, ALE_FWSTATE_FWONLY);
+ cpsw_ale_entry_set(ale_entry, ALE_PORT_MASK, ALE_PORT_MASK_ALL);
+ cpsw_ale_write_entry(sc, 1, ale_entry);
+
+ /*
+ * SIOCDELMULTI doesn't specify the particular address
+ * being removed, so we have to remove all and rebuild.
+ */
+ if (purge)
+ cpsw_ale_remove_all_mc_entries(sc);
+
+ /* Set other multicast addrs desired. */
+ LIST_FOREACH(ifma, &ac->ac_multiaddrs, enm_list) {
+ cpsw_ale_mc_entry_set(sc, ALE_PORT_MASK_ALL, ifma->enm_addrlo);
+ }
+
+ return 0;
}
Index: if_cpswreg.h
===================================================================
RCS file: /cvs/src/sys/arch/armv7/omap/if_cpswreg.h,v
retrieving revision 1.5
diff -u -p -r1.5 if_cpswreg.h
--- if_cpswreg.h 15 Nov 2013 14:31:52 -0000 1.5
+++ if_cpswreg.h 6 Nov 2014 10:32:07 -0000
@@ -39,6 +39,7 @@
#define CPSW_SS_SOFT_RESET (CPSW_SS_OFFSET + 0x08)
#define CPSW_SS_STAT_PORT_EN (CPSW_SS_OFFSET + 0x0C)
#define CPSW_SS_PTYPE (CPSW_SS_OFFSET + 0x10)
+#define CPSW_SS_RGMII_CTL (CPSW_SS_OFFSET + 0x88)
#define CPSW_PORT_OFFSET 0x0100
#define CPSW_PORT_P_TX_PRI_MAP(p) (CPSW_PORT_OFFSET + 0x118 + ((p-1) *
0x100))
@@ -47,6 +48,8 @@
#define CPSW_PORT_P_SA_LO(p) (CPSW_PORT_OFFSET + 0x120 + ((p-1) *
0x100))
#define CPSW_PORT_P_SA_HI(p) (CPSW_PORT_OFFSET + 0x124 + ((p-1) *
0x100))
+#define CPSW_GMII_SEL 0x0650
+
#define CPSW_CPDMA_OFFSET 0x0800
#define CPSW_CPDMA_TX_CONTROL (CPSW_CPDMA_OFFSET + 0x04)
#define CPSW_CPDMA_TX_TEARDOWN (CPSW_CPDMA_OFFSET + 0x08)
@@ -112,7 +115,7 @@
#define CPSW_WR_C_RX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x44)
#define CPSW_WR_C_TX_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x48)
#define CPSW_WR_C_MISC_STAT(p) (CPSW_WR_OFFSET + (0x10 * (p)) + 0x4C)
-#define CPSW_MISC_HOST_PEND 0x0004
+#define CPSW_MISC_HOST_PEND 0x0004
#define CPSW_CPPI_RAM_OFFSET 0x2000
@@ -138,5 +141,83 @@ struct cpsw_cpdma_bd {
#define CPSW_INTROFF_RX 1
#define CPSW_INTROFF_TX 2
#define CPSW_INTROFF_MISC 3
+
+ /* MDIOCONTROL Register Field */
+#define MDIOCTL_IDLE (1<<31)
+#define MDIOCTL_ENABLE (1<<30)
+#define MDIOCTL_HIGHEST_USER_CHANNEL(val) ((0xf & (val)) << 24)
+#define MDIOCTL_PREAMBLE (1<<20)
+#define MDIOCTL_FAULT (1<<19)
+#define MDIOCTL_FAULTENB (1<<18)
+#define MDIOCTL_INTTESTENB (1<<17)
+#define MDIOCTL_CLKDIV(val) (0xff & (val))
+
+/* ALE Control Register Field */
+#define ALECTL_ENABLE_ALE (1<<31)
+#define ALECTL_CLEAR_TABLE (1<<30)
+#define ALECTL_AGE_OUT_NOW (1<<29)
+#define ALECTL_EN_P0_UNI_FLOOD (1<<8)
+#define ALECTL_LEARN_NO_VID (1<<7)
+#define ALECTL_EN_VID0_MODE (1<<6)
+#define ALECTL_ENABLE_OUI_DENY (1<<5)
+#define ALECTL_BYPASS (1<<4)
+#define ALECTL_RATE_LIMIT_TX (1<<3)
+#define ALECTL_VLAN_AWARE (1<<2)
+#define ALECTL_ENABLE_AUTH_MODE (1<<1)
+#define ALECTL_ENABLE_RATE_LIMIT (1<<0)
+
+/* GMII_SEL Register Field */
+#define GMIISEL_RMII2_IO_CLK_EN (1<<7)
+#define GMIISEL_RMII1_IO_CLK_EN (1<<6)
+#define GMIISEL_RGMII2_IDMODE (1<<5)
+#define GMIISEL_RGMII1_IDMODE (1<<4)
+#define GMIISEL_GMII2_SEL(val) ((0x3 & (val)) << 2)
+#define GMIISEL_GMII1_SEL(val) ((0x3 & (val)) << 0)
+#define GMII_MODE 0
+#define RMII_MODE 1
+#define RGMII_MODE 2
+
+/* Sliver MACCONTROL Register Field */
+#define SLMACCTL_RX_CMF_EN (1<<24)
+#define SLMACCTL_RX_CSF_EN (1<<23)
+#define SLMACCTL_RX_CEF_EN (1<<22)
+#define SLMACCTL_TX_SHORT_GAP_LIM_EN (1<<21)
+#define SLMACCTL_EXT_EN (1<<18)
+#define SLMACCTL_GIG_FORCE (1<<17)
+#define SLMACCTL_IFCTL_B (1<<16)
+#define SLMACCTL_IFCTL_A (1<<15)
+#define SLMACCTL_CMD_IDLE (1<<11)
+#define SLMACCTL_TX_SHORT_GAP_EN (1<<10)
+#define SLMACCTL_GIG (1<<7)
+#define SLMACCTL_TX_PACE (1<<6)
+#define SLMACCTL_GMII_EN (1<<5)
+#define SLMACCTL_TX_FLOW_EN (1<<4)
+#define SLMACCTL_RX_FLOW_EN (1<<3)
+#define SLMACCTL_MTEST (1<<2)
+#define SLMACCTL_LOOPBACK (1<<1)
+#define SLMACCTL_FULLDUPLEX (1<<0)
+
+/* ALE Address Table Entry Field */
+typedef enum {
+ ALE_ENTRY_TYPE,
+ ALE_MCAST_FWD_STATE,
+ ALE_PORT_MASK,
+ ALE_PORT_NUMBER,
+} ale_entry_filed_t;
+
+#define ALE_TYPE_FREE 0
+#define ALE_TYPE_ADDRESS 1
+#define ALE_TYPE_VLAN 2
+#define ALE_TYPE_VLAN_ADDRESS 3
+
+/*
+ * The port state(s) required for the received port on a destination address
+ * lookup in order for the multicast packet to be forwarded to the transmit
+ * port(s)
+ */
+#define ALE_FWSTATE_ALL 1 /* Blocking/Forwarding/Learning
*/
+#define ALE_FWSTATE_NOBLOCK 2 /* Forwarding/Learning */
+#define ALE_FWSTATE_FWONLY 3 /* Forwarding */
+#define ALE_PORT_MASK_ALL 7
#endif /*_IF_CPSWREG_H */
On Thu, Nov 06, 2014 at 10:07:37AM +0100, Mérindol Bernard wrote:
> Hi,
>
> Very thank for your test.
>
> I'm sad because it's not just my changes are involved.
> I think is not in ALE (but I'll make the change to set the lookup table in
> ALE), but is the interupt handling.
>
> Best regards
> Bernard
>
> > On 6 nov. 2014, at 09:55, Jonathan Gray <j...@jsg.id.au> wrote:
> >
> > Here is what I see connecting from a bbb on nfs root via
> > a 100Mb switch to another host:
> >
> > tcpbench
> > tcp 5.2 Mbps
> > udp 11.6 Mbps 990 pps
> >
> > iperf
> > tcp 5.29 Mbits/sec
> > udp 1.05 Mbits/sec
> >
> > I'm not sure why udp differs here.
> >
> > Connecting from linux that was preinstalled on the emmc:
> >
> > iperf
> > tcp 92.5 Mbits/sec
> > udp 1.05 Mbits/sec
> >
> > Perhaps the switch frontend/ALE configuration is not set
> > up correctly? I'm sure you must have read a bit about that
> > when looking into adding support for the other port.
> >
> > It looks like there is not a clean seperation of registers/interrupts/dma
> > for the different ports which is annoying.
> >
> > The driver in OpenBSD does not attempt to do interrupt mitigation either.
> >
> > Though perhaps with such a large difference something more fundamental
> > like the processor cache/pmap/frequency handling could be implicated?
> >
> > On Tue, Nov 04, 2014 at 08:42:20AM +0100, Mérindol Bernard wrote:
> >> Hi Jonathan,
> >>
> >> Thank for your answer.
> >>
> >> I have re build my OpenBSD with Artheros Phy support
> >>
> >> com0: console
> >> cpsw0 at omap0: version 1.12 (0), address d4:94:a1:84:28:f2
> >> atphy0 at cpsw0 phy 0: F1 10/100/1000 PHY, rev. 4
> >> atphy1 at cpsw0 phy 1: F1 10/100/1000 PHY, rev. 4
> >> scsibus0 at sdmmc0: 2 targets, initiator 0
> >> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, Drive #01, > SCSI2 0/direct fixed
> >>
> >>
> >> But the result is same. I try to install last version of NetBSD to test.
> >>
> >> If you or an other person have BeaglBoard with OpenBSD installed is it
> >> possible to send to me the result of this command.
> >>
> >> On OpenBsd
> >> nc -l 1234 > /dev/null
> >>
> >> on other host (with XXBSD example OS X);
> >> mkfile 100m CentM
> >>
> >> date;nc <@IP of your BeagleBoard> 1234 < CentM;date
> >>
> >> If you use Linux try with this command to create 100M file.
> >> dd if=/dev/zero of=CentM bs=100M count=1
> >>
> >> Thank
> >> Bernard Merindol
> >>
> >> PS: send also the result of ifconfig cpsw0
> >>
> >>
> >> On 3 nov. 2014, at 14:13, Jonathan Gray <j...@jsg.id.au> wrote:
> >>>
> >>>
> >>> You have a different phy to the beaglebone boards.
> >>> It seems to be an Atheros phy that would be handled by atphy(4)
> >>> if it were added to the kernel configuration.
> >>>
> >>> I doubt that would make much of a difference though.
> >>>
> >>> rev 1.5 in NetBSD which programs the multicast filter could be
> >>> interesting
> >>>
> >>> http://cvsweb.netbsd.org/bsdweb.cgi/src/sys/arch/arm/omap/if_cpsw.c?only_with_tag=MAIN
> >>>
> >>> "Make cpsw driver work without uboot support
> >>>
> >>> On some eval boards such as BeagleBone, the cpsw device is initialized
> >>> rightly by the uboot of the boards so that the cpsw driver doesn't need
> >>> to do some initializations but works fine.
> >>>
> >>> The patch adds initializations to make the driver work solely. It also
> >>> adds support for 1000BaseT (RGMII) PHY that is equipped on some boards,
> >>> e.g., CKB-3352."
> >>>
> >>> It seems the phy might need special handling according to
> >>> http://processors.wiki.ti.com/index.php/AM335x_General_Purpose_EVM_HW_User_Guide#Gbit_Ethernet
> >>>
> >>> "Note: The GP EVM PCB does not support external delay for the clock
> >>> signals on the RGMII interface. The AR8031A PHY can be setup to use
> >>> internal clock delay mode once booting is complete. Therefore there may
> >>> be problems in function/performance when booting in Gb mode or when
> >>> running Gb Ethernet Mode before the AR8031A PHY is configured properly.
> >>> See the EVM Errata."
> >>>
> >>> Which sounds rather like the cpsw specific hack in
> >>> http://cvsweb.netbsd.org/bsdweb.cgi/~checkout~/src/sys/dev/mii/micphy.c?rev=1.3
> >>>
> >>> On Mon, Nov 03, 2014 at 12:01:39PM +0100, Mérindol Bernard wrote:
> >>>> Hi All,
> >>>>
> >>>> I works with AM335x Starter Kit from TI, I modify the cpsw driver to
> >>>> works with 2 ports (cpsw0 and cpsw1).
> >>>>
> >>>> Before this modification I have tested the performance on native driver
> >>>> with this command.
> >>>>
> >>>> on OBSD
> >>>> nc -l 1234 > /dev/null
> >>>>
> >>>>
> >>>> on host connected by switch 100Mbit/s full duplex (MAC OX 10.10)
> >>>>
> >>>> nc 192.168.169.62 1234 < CentM
> >>>>
> >>>> where CentM il file with 100MByte (created with makefile 100m CentM).
> >>>>
> >>>> On BSD5.5 or 5.6 the time for this transfert is 93s = 8,6 Mbit/s
> >>>>
> >>>> I have try the same transfert with Linux (on same board) the time is 9s
> >>>> = 89Mbit/s
> >>>>
> >>>> The performance of transfert on OBSD is poor why ?
> >>>>
> >>>> Driver ?
> >>>> Kernel ?
> >>>> Or mistake on my configuration.
> >>>>
> >>>> I need ARM card with 2 ethernets (giga) Port to configure in routing
> >>>> from port 1 to port 2. I hope 200Mbit/s (linux performance) for this
> >>>> routing.
> >>>>
> >>>> Thank for your help.
> >>>> Bernard
> >>>> _________________________________
> >>>> result of ifconfig
> >>>> # ifconfig cpsw0
> >>>> cpsw0: flags=28843<UP,BROADCAST,RUNNING,SIMPLEX,MULTICAST,NOINET6> mtu
> >>>> 1500
> >>>> lladdr d4:94:a1:84:28:f2
> >>>> priority: 0
> >>>> groups: egress
> >>>> media: Ethernet 100baseTX full-duplex
> >>>> status: active
> >>>> inet 192.168.169.62 netmask 0xffffff00 broadcast 192.168.169.255
> >>>>
> >>>>
> >>>> __________________________________
> >>>> result of dmessg
> >>>> # dmesg
> >>>> OpenBSD 5.6-current (GENERIC-OMAP) #0: Tue Oct 28 01:01:45 AEDT 2014
> >>>> j...@armv7.jsg.id.au:/usr/src/sys/arch/armv7/compile/GENERIC-OMAP
> >>>> real mem = 268435456 (256MB)
> >>>> avail mem = 255725568 (243MB)
> >>>> warning: no entropy supplied by boot loader
> >>>> mainbus0 at root
> >>>> cpu0 at mainbus0: ARM Cortex A8 R3 rev 2 (ARMv7 core)
> >>>> cpu0: DC enabled IC enabled WB disabled EABT branch prediction enabled
> >>>> cpu0: 32KB(64b/l,4way) I-cache, 32KB(64b/l,4way) wr-back D-cache
> >>>> omap0 at mainbus0: BeagleBone
> >>>> prcm0 at omap0 rev 0.2
> >>>> sitaracm0 at omap0: control module, rev 1.0
> >>>> intc0 at omap0 rev 5.0
> >>>> edma0 at omap0 rev 0.0
> >>>> dmtimer0 at omap0 rev 3.1
> >>>> dmtimer1 at omap0 rev 3.1
> >>>> omdog0 at omap0 rev 0.1
> >>>> omgpio0 at omap0: rev 0.1
> >>>> gpio0 at omgpio0: 32 pins
> >>>> omgpio1 at omap0: rev 0.1
> >>>> gpio1 at omgpio1: 32 pins
> >>>> omgpio2 at omap0: rev 0.1
> >>>> gpio2 at omgpio2: 32 pins
> >>>> omgpio3 at omap0: rev 0.1
> >>>> gpio3 at omgpio3: 32 pins
> >>>> omap0: device tiiic unit 0 not configured
> >>>> omap0: device tiiic unit 1 not configured
> >>>> omap0: device tiiic unit 2 not configured
> >>>> ommmc0 at omap0
> >>>> sdmmc0 at ommmc0
> >>>> ommmc1 at omap0
> >>>> sdmmc1 at ommmc1
> >>>> com0 at omap0: ti16750, 64 byte fifo
> >>>> com0: console
> >>>> cpsw0 at omap0: version 1.12 (0), address d4:94:a1:84:28:f2
> >>>> ukphy0 at cpsw0 phy 0: Generic IEEE 802.3u media interface, rev. 4: OUI
> >>>> 0x001374, model 0x0007
> >>>> ukphy1 at cpsw0 phy 1: Generic IEEE 802.3u media interface, rev. 4: OUI
> >>>> 0x001374, model 0x0007
> >>>> scsibus0 at sdmmc0: 2 targets, initiator 0
> >>>> sd0 at scsibus0 targ 1 lun 0: <SD/MMC, Drive #01, > SCSI2 0/direct fixed
> >>>> sd0: 3781MB, 512 bytes/sector, 7744512 sectors
> >>>> sdmmc1: can't enable card
> >>>> vscsi0 at root
> >>>> scsibus1 at vscsi0: 256 targets
> >>>> softraid0 at root
> >>>> scsibus2 at softraid0: 256 targets
> >>>> boot device: sd0
> >>>> root on sd0a (853680ee25c0e223.a) swap on sd0b dump on sd0b
> >>>> WARNING: CHECK AND RESET THE DATE!
> >>>>
> >>>>
> >>>> __________________________________________
> >>>> Bernard M. Merindol, Grenoble France
> >>>> bern...@merindol.org GSM: +33-6-08-75-03-52
> >>>>
> >>
> >> __________________________________________
> >> Bernard M. Merindol, Grenoble France
> >> bern...@merindol.org GSM: +33-6-08-75-03-52
> >>
>
> __________________________________________
> Bernard M. Merindol, Grenoble France
> bern...@merindol.org GSM: +33-6-08-75-03-52
