Re: [PATCH] drm/amdgpu: Add xcc instance parameter to *REG32_SOC15_IP_NO_KIQ (v3)

[Lazar, Lijo]

On 10/28/2023 1:36 AM, Victor Lu wrote:
The WREG32/RREG32_SOC15_IP_NO_KIQ call is using XCC0's RLCG interface
when programming other XCCs.

Add xcc instance parameter to them.

v3: xcc not needed for MMMHUB

v2: rebase

Signed-off-by: Victor Lu <victorchengchi...@amd.com>
---
  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c     | 16 ++++++++--------
  drivers/gpu/drm/amd/amdgpu/soc15_common.h |  6 +++---
  2 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3a1050344b59..0ab9c554da78 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -856,9 +856,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
                for (j = 0; j < adev->usec_timeout; j++) {
                        /* a read return value of 1 means semaphore acquire */
                        if (vmhub >= AMDGPU_MMHUB0(0))
-                               tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem);
+                               tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0);

Since rlc reg access ctrl is populated using GET_INST(GC, xcc_id), use 
GET_INST(GC, 0) to be consistent.

Thanks,
Lijo
                        else
-                               tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem);
+                               tmp = RREG32_SOC15_IP_NO_KIQ(GC, sem, vmhub);
                        if (tmp & 0x1)
                                break;
                        udelay(1);
@@ -869,9 +869,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
        }
  
  	if (vmhub >= AMDGPU_MMHUB0(0))
-               WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req);
+               WREG32_SOC15_IP_NO_KIQ(MMHUB, req, inv_req, 0);
        else
-               WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req);
+               WREG32_SOC15_IP_NO_KIQ(GC, req, inv_req, vmhub);
  
  	/*
         * Issue a dummy read to wait for the ACK register to
@@ -884,9 +884,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
  
  	for (j = 0; j < adev->usec_timeout; j++) {
                if (vmhub >= AMDGPU_MMHUB0(0))
-                       tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack);
+                       tmp = RREG32_SOC15_IP_NO_KIQ(MMHUB, ack, 0);
                else
-                       tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack);
+                       tmp = RREG32_SOC15_IP_NO_KIQ(GC, ack, vmhub);
                if (tmp & (1 << vmid))
                        break;
                udelay(1);
@@ -899,9 +899,9 @@ static void gmc_v9_0_flush_gpu_tlb(struct amdgpu_device 
*adev, uint32_t vmid,
                 * write with 0 means semaphore release
                 */
                if (vmhub >= AMDGPU_MMHUB0(0))
-                       WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0);
+                       WREG32_SOC15_IP_NO_KIQ(MMHUB, sem, 0, 0);
                else
-                       WREG32_SOC15_IP_NO_KIQ(GC, sem, 0);
+                       WREG32_SOC15_IP_NO_KIQ(GC, sem, 0, vmhub);
        }
  
  	spin_unlock(&adev->gmc.invalidate_lock);
diff --git a/drivers/gpu/drm/amd/amdgpu/soc15_common.h 
b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
index da683afa0222..c75e9cd5c98b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc15_common.h
+++ b/drivers/gpu/drm/amd/amdgpu/soc15_common.h
@@ -69,7 +69,7 @@
  
  #define RREG32_SOC15_IP(ip, reg) __RREG32_SOC15_RLC__(reg, 0, ip##_HWIP, 0)
  
-#define RREG32_SOC15_IP_NO_KIQ(ip, reg) __RREG32_SOC15_RLC__(reg, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
+#define RREG32_SOC15_IP_NO_KIQ(ip, reg, inst) __RREG32_SOC15_RLC__(reg, 
AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
  
  #define RREG32_SOC15_NO_KIQ(ip, inst, reg) \
        __RREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] 
+ reg, \
@@ -86,8 +86,8 @@
  #define WREG32_SOC15_IP(ip, reg, value) \
         __WREG32_SOC15_RLC__(reg, value, 0, ip##_HWIP, 0)
  
-#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value) \
-        __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, 0)
+#define WREG32_SOC15_IP_NO_KIQ(ip, reg, value, inst) \
+        __WREG32_SOC15_RLC__(reg, value, AMDGPU_REGS_NO_KIQ, ip##_HWIP, inst)
  
  #define WREG32_SOC15_NO_KIQ(ip, inst, reg, value) \
        __WREG32_SOC15_RLC__(adev->reg_offset[ip##_HWIP][inst][reg##_BASE_IDX] 
+ reg, \