Via this, the logic for adding/dropping the support for some specific
sysfs interface can be greatly simplified.
Signed-off-by: Evan Quan <evan.q...@amd.com>
Change-Id: Ica470cb8afd5b6cf7cc2a47b8310746b6c3b6f97
---
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c | 9 ++
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 115 +++++++++++++++------
drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h | 37 +++++++
drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h | 16 +--
4 files changed, 141 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
index 2017b3466612..b1943336551f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
@@ -3639,6 +3639,15 @@ int amdgpu_device_init(struct amdgpu_device *adev,
ratelimit_state_init(&adev->throttling_logging_rs, (60 - 1) * HZ, 1);
ratelimit_set_flags(&adev->throttling_logging_rs,
RATELIMIT_MSG_ON_RELEASE);
+ /*
+ * At default, all sysfs interfaces are claimed to be supported.
+ * And every sysfs interface is readable and writable. However,
+ * each ASIC can have its own setting by overriding these.
+ */
+ adev->pm.sysfs_if_supported = AMD_SYSFS_IF_BITMASK_ALL_SUPPORTED;
+ for (i = 0; i < AMD_MAX_NUMBER_OF_SYSFS_IF_SUPPORTED; i++)
+ adev->pm.sysfs_if_attr_mode[i] = S_IRUGO | S_IWUGO;
+
/* Registers mapping */
/* TODO: block userspace mapping of io register */
if (adev->asic_type >= CHIP_BONAIRE) {
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index 236657eece47..fb6a7d45693a 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -1913,36 +1913,92 @@ static int ss_bias_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
}
static struct amdgpu_device_attr amdgpu_device_attrs[] = {
- AMDGPU_DEVICE_ATTR_RW(power_dpm_state,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(pp_num_states,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(pp_cur_state,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_force_state,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_table,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,
ATTR_FLAG_BASIC),
- AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,
ATTR_FLAG_BASIC),
- AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,
ATTR_FLAG_BASIC),
- AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(pcie_bw,
ATTR_FLAG_BASIC),
- AMDGPU_DEVICE_ATTR_RW(pp_features,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(unique_id,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(gpu_metrics,
ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
- AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,
ATTR_FLAG_BASIC,
+ AMDGPU_DEVICE_ATTR_RW(power_dpm_state,
+ AMD_SYSFS_IF_POWER_DPM_STATE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,
+
AMD_SYSFS_IF_POWER_DPM_FORCE_PERFORMANCE_LEVEL_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(pp_num_states,
+ AMD_SYSFS_IF_PP_NUM_STATES_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(pp_cur_state,
+ AMD_SYSFS_IF_PP_CUR_STATE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_force_state,
+ AMD_SYSFS_IF_PP_FORCE_STATE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_table,
+ AMD_SYSFS_IF_PP_TABLE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,
+ AMD_SYSFS_IF_PP_DPM_SCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,
+ AMD_SYSFS_IF_PP_DPM_MCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,
+ AMD_SYSFS_IF_PP_DPM_SOCCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,
+ AMD_SYSFS_IF_PP_DPM_FCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_vclk,
+ AMD_SYSFS_IF_PP_DPM_VCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_dclk,
+ AMD_SYSFS_IF_PP_DPM_DCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,
+ AMD_SYSFS_IF_PP_DPM_DCEFCLK_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,
+ AMD_SYSFS_IF_PP_DPM_PCIE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,
+ AMD_SYSFS_IF_PP_SCLK_OD_BIT,
+ ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,
+ AMD_SYSFS_IF_PP_MCLK_OD_BIT,
+ ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,
+ AMD_SYSFS_IF_PP_POWER_PROFILE_MODE_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,
+ AMD_SYSFS_IF_PP_OD_CLK_VOLTAGE_BIT,
+ ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,
+ AMD_SYSFS_IF_GPU_BUSY_PERCENT_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,
+ AMD_SYSFS_IF_MEM_BUSY_PERCENT_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(pcie_bw,
+ AMD_SYSFS_IF_PCIE_BW_BIT,
+ ATTR_FLAG_BASIC),
+ AMDGPU_DEVICE_ATTR_RW(pp_features,
+ AMD_SYSFS_IF_PP_FEATURES_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(unique_id,
+ AMD_SYSFS_IF_UNIQUE_ID_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,
+ AMD_SYSFS_IF_THERMAL_THROTTLING_LOGGING_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(gpu_metrics,
+ AMD_SYSFS_IF_GPU_METRICS_BIT,
+ ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
+ AMDGPU_DEVICE_ATTR_RO(smartshift_apu_power,
+ AMD_SYSFS_IF_SMARTSHIFT_APU_POWER_BIT,
+ ATTR_FLAG_BASIC,
.attr_update = ss_power_attr_update),
- AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,
ATTR_FLAG_BASIC,
+ AMDGPU_DEVICE_ATTR_RO(smartshift_dgpu_power,
+ AMD_SYSFS_IF_SMARTSHIFT_DGPU_POWER_BIT,
+ ATTR_FLAG_BASIC,
.attr_update = ss_power_attr_update),
- AMDGPU_DEVICE_ATTR_RW(smartshift_bias,
ATTR_FLAG_BASIC,
+ AMDGPU_DEVICE_ATTR_RW(smartshift_bias,
+ AMD_SYSFS_IF_SMARTSHIFT_BIAS_BIT,
+ ATTR_FLAG_BASIC,
.attr_update = ss_bias_attr_update),
};
@@ -1954,7 +2010,8 @@ static int default_attr_update(struct amdgpu_device
*adev, struct amdgpu_device_
uint32_t gc_ver = adev->ip_versions[GC_HWIP][0];
const char *attr_name = dev_attr->attr.name;
- if (!(attr->flags & mask)) {
+ if (!(attr->flags & mask) ||
+ !(AMD_SYSFS_IF_BITMASK(attr->if_bit) &
adev->pm.sysfs_if_supported)) {
*states = ATTR_STATE_UNSUPPORTED;
return 0;
}
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
index cb5b9df78b4d..bbee77087226 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_dpm.h
@@ -312,6 +312,39 @@ struct config_table_setting
uint16_t fclk_average_tau;
};
+/* Bitmasks for controlling which Sysfs interface to support */
+#define AMD_SYSFS_IF_POWER_DPM_STATE_BIT 0U
+#define AMD_SYSFS_IF_POWER_DPM_FORCE_PERFORMANCE_LEVEL_BIT 1U
+#define AMD_SYSFS_IF_PP_NUM_STATES_BIT 2U
+#define AMD_SYSFS_IF_PP_CUR_STATE_BIT 3U
+#define AMD_SYSFS_IF_PP_FORCE_STATE_BIT 4U
+#define AMD_SYSFS_IF_PP_TABLE_BIT 5U
+#define AMD_SYSFS_IF_PP_DPM_SCLK_BIT 6U
+#define AMD_SYSFS_IF_PP_DPM_MCLK_BIT 7U
+#define AMD_SYSFS_IF_PP_DPM_SOCCLK_BIT 8U
+#define AMD_SYSFS_IF_PP_DPM_FCLK_BIT 9U
+#define AMD_SYSFS_IF_PP_DPM_VCLK_BIT 10U
+#define AMD_SYSFS_IF_PP_DPM_DCLK_BIT 11U
+#define AMD_SYSFS_IF_PP_DPM_DCEFCLK_BIT 12U
+#define AMD_SYSFS_IF_PP_DPM_PCIE_BIT 13U
+#define AMD_SYSFS_IF_PP_SCLK_OD_BIT 14U
+#define AMD_SYSFS_IF_PP_MCLK_OD_BIT 15U
+#define AMD_SYSFS_IF_PP_POWER_PROFILE_MODE_BIT 16U
+#define AMD_SYSFS_IF_PP_OD_CLK_VOLTAGE_BIT 17U
+#define AMD_SYSFS_IF_GPU_BUSY_PERCENT_BIT 18U
+#define AMD_SYSFS_IF_MEM_BUSY_PERCENT_BIT 19U
+#define AMD_SYSFS_IF_PCIE_BW_BIT 20U
+#define AMD_SYSFS_IF_PP_FEATURES_BIT 21U
+#define AMD_SYSFS_IF_UNIQUE_ID_BIT 22U
+#define AMD_SYSFS_IF_THERMAL_THROTTLING_LOGGING_BIT 23U
+#define AMD_SYSFS_IF_GPU_METRICS_BIT 24U
+#define AMD_SYSFS_IF_SMARTSHIFT_APU_POWER_BIT 25U
+#define AMD_SYSFS_IF_SMARTSHIFT_DGPU_POWER_BIT 26U
+#define AMD_SYSFS_IF_SMARTSHIFT_BIAS_BIT 27U
+#define AMD_MAX_NUMBER_OF_SYSFS_IF_SUPPORTED 64U
+#define AMD_SYSFS_IF_BITMASK(if_bit) (1ULL <<
(if_bit))
+#define AMD_SYSFS_IF_BITMASK_ALL_SUPPORTED ULLONG_MAX
+
struct amdgpu_pm {
struct mutex mutex;
u32 current_sclk;
@@ -364,6 +397,10 @@ struct amdgpu_pm {
struct config_table_setting config_table;
/* runtime mode */
enum amdgpu_runpm_mode rpm_mode;
+
+ /* bitmasks for clarifying which sysfs interfaces supported */
+ uint64_t sysfs_if_supported;
+ umode_t
sysfs_if_attr_mode[AMD_MAX_NUMBER_OF_SYSFS_IF_SUPPORTED];
};
int amdgpu_dpm_read_sensor(struct amdgpu_device *adev, enum amd_pp_sensors
sensor,
diff --git a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h
b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h
index 52045ad59bed..bffc1bc94641 100644
--- a/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h
+++ b/drivers/gpu/drm/amd/pm/inc/amdgpu_pm.h
@@ -46,6 +46,7 @@ enum amdgpu_device_attr_states {
struct amdgpu_device_attr {
struct device_attribute dev_attr;
+ uint64_t if_bit;
enum amdgpu_device_attr_flags flags;
int (*attr_update)(struct amdgpu_device *adev, struct
amdgpu_device_attr *attr,
uint32_t mask, enum amdgpu_device_attr_states
*states);
@@ -60,24 +61,25 @@ struct amdgpu_device_attr_entry {
#define to_amdgpu_device_attr(_dev_attr) \
container_of(_dev_attr, struct amdgpu_device_attr, dev_attr)
-#define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _flags, ...) \
+#define __AMDGPU_DEVICE_ATTR(_name, _mode, _show, _store, _bit, _flags, ...)
\
{ .dev_attr = __ATTR(_name, _mode, _show, _store), \
+ .if_bit = _bit, \
.flags = _flags, \
##__VA_ARGS__, }
-#define AMDGPU_DEVICE_ATTR(_name, _mode, _flags, ...) \
+#define AMDGPU_DEVICE_ATTR(_name, _mode, _bit, _flags, ...) \
__AMDGPU_DEVICE_ATTR(_name, _mode, \
amdgpu_get_##_name, amdgpu_set_##_name, \
- _flags, ##__VA_ARGS__)
+ _bit, _flags, ##__VA_ARGS__)
-#define AMDGPU_DEVICE_ATTR_RW(_name, _flags, ...) \
+#define AMDGPU_DEVICE_ATTR_RW(_name, _bit, _flags, ...) \
AMDGPU_DEVICE_ATTR(_name, S_IRUGO | S_IWUSR, \
- _flags, ##__VA_ARGS__)
+ _bit, _flags, ##__VA_ARGS__)
-#define AMDGPU_DEVICE_ATTR_RO(_name, _flags, ...) \
+#define AMDGPU_DEVICE_ATTR_RO(_name, _bit, _flags, ...) \
__AMDGPU_DEVICE_ATTR(_name, S_IRUGO, \
amdgpu_get_##_name, NULL, \
- _flags, ##__VA_ARGS__)
+ _bit, _flags, ##__VA_ARGS__)
int amdgpu_pm_sysfs_init(struct amdgpu_device *adev);
int amdgpu_pm_virt_sysfs_init(struct amdgpu_device *adev);
--
2.34.1
