[PATCH 17/29] drm/amd/display: fix unbounded requesting for high pixel rate modes on dcn315

[Tom Chung]

From: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>

Unbounded requesting is getting configured for odm mode calculations which
is incorrect. This change checks whether mode requires odm ahead of time.

Reviewed-by: Jun Lei <jun....@amd.com>
Acked-by: Tom Chung <chiahsuan.ch...@amd.com>
Signed-off-by: Dmytro Laktyushkin <dmytro.laktyush...@amd.com>
---
 drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c | 4 +++-
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c    | 5 +++++
 drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h    | 1 +
 3 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c 
b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
index 2a5227330513..2d05e8d843c9 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn315/dcn315_resource.c
@@ -1706,7 +1706,9 @@ static int dcn315_populate_dml_pipes_from_context(
                        dc->config.enable_4to1MPC = true;
                        context->bw_ctx.dml.ip.det_buffer_size_kbytes =
                                        (max_usable_det / 
DCN3_15_CRB_SEGMENT_SIZE_KB / 4) * DCN3_15_CRB_SEGMENT_SIZE_KB;
-               } else if (!is_dual_plane(pipe->plane_state->format) && 
pipe->plane_state->src_rect.width <= 5120) {
+               } else if (!is_dual_plane(pipe->plane_state->format)
+                               && pipe->plane_state->src_rect.width <= 5120
+                               && pipe->stream->timing.pix_clk_100hz < 
dcn_get_max_non_odm_pix_rate_100hz(&dc->dml.soc)) {
                        /* Limit to 5k max to avoid forced pipe split when 
there is not enough detile for swath */
                        context->bw_ctx.dml.ip.det_buffer_size_kbytes = 192;
                        pipes[0].pipe.src.unbounded_req_mode = true;
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
index 4cdad8674b8e..12b23bd50e19 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.c
@@ -807,3 +807,8 @@ void dcn316_update_bw_bounding_box(struct dc *dc, struct 
clk_bw_params *bw_param
        else
                dml_init_instance(&dc->dml, &dcn3_16_soc, &dcn3_16_ip, 
DML_PROJECT_DCN31_FPGA);
 }
+
+int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st 
*soc)
+{
+       return soc->clock_limits[0].dispclk_mhz * 10000.0 / (1.0 + 
soc->dcn_downspread_percent / 100.0);
+}
diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h 
b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
index b0b2ba9df57a..687d3522cc33 100644
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn31/dcn31_fpu.h
@@ -46,6 +46,7 @@ void dcn31_calculate_wm_and_dlg_fp(
 void dcn31_update_bw_bounding_box(struct dc *dc, struct clk_bw_params 
*bw_params);
 void dcn315_update_bw_bounding_box(struct dc *dc, struct clk_bw_params 
*bw_params);
 void dcn316_update_bw_bounding_box(struct dc *dc, struct clk_bw_params 
*bw_params);
+int dcn_get_max_non_odm_pix_rate_100hz(struct _vcs_dpi_soc_bounding_box_st 
*soc);
 
 int dcn31x_populate_dml_pipes_from_context(struct dc *dc,
                                          struct dc_state *context,
-- 
2.25.1