[PATCH 07/29] drm/amd/display: Program pipes for ODM when removing planes

[Tom Chung]

From: Dillon Varone <dillon.var...@amd.com>

[WHY?]
Software state expects pipes to be configured for ODM, but due to the transition
occurring on a plane disable, the ODM enablement code is not run.

[HOW?]
Update ODM when removing a plane, and dynamic ODM is active. Also acquire pipe
lock when removing a plane.

Reviewed-by: Alvin Lee <alvin.l...@amd.com>
Acked-by: Tom Chung <chiahsuan.ch...@amd.com>
Signed-off-by: Dillon Varone <dillon.var...@amd.com>
---
 .../gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c |  4 +++-
 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c    | 11 +++++++++++
 2 files changed, 14 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 
b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
index 11e4c4e46947..587b04b8712d 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c
@@ -97,10 +97,12 @@ void dcn10_lock_all_pipes(struct dc *dc,
        bool lock)
 {
        struct pipe_ctx *pipe_ctx;
+       struct pipe_ctx *old_pipe_ctx;
        struct timing_generator *tg;
        int i;
 
        for (i = 0; i < dc->res_pool->pipe_count; i++) {
+               old_pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
                pipe_ctx = &context->res_ctx.pipe_ctx[i];
                tg = pipe_ctx->stream_res.tg;
 
@@ -110,7 +112,7 @@ void dcn10_lock_all_pipes(struct dc *dc,
                 */
                if (pipe_ctx->top_pipe ||
                    !pipe_ctx->stream ||
-                   !pipe_ctx->plane_state ||
+                   (!pipe_ctx->plane_state && !old_pipe_ctx->plane_state) ||
                    !tg->funcs->is_tg_enabled(tg))
                        continue;
 
diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c 
b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index b465a83bde6f..64fcb378594f 100644
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1834,6 +1834,17 @@ void dcn20_program_front_end_for_ctx(
                        context->stream_status[0].plane_count > 1) {
                        
pipe->plane_res.hubp->funcs->hubp_wait_pipe_read_start(pipe->plane_res.hubp);
                }
+
+               /* when dynamic ODM is active, pipes must be reconfigured when 
all planes are
+                * disabled, as some transitions will leave software and 
hardware state
+                * mismatched.
+                */
+               if (dc->debug.enable_single_display_2to1_odm_policy &&
+                       pipe->stream &&
+                       pipe->update_flags.bits.disable &&
+                       !pipe->prev_odm_pipe &&
+                       hws->funcs.update_odm)
+                       hws->funcs.update_odm(dc, context, pipe);
        }
 }
 
-- 
2.25.1