This is a note to let you know that I've just added the patch titled
drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
to the 6.12-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amd-display-adjust-dce-8-10-clock-don-t-overclock-by-15.patch
and it can be found in the queue-6.12 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree,
please let <[email protected]> know about it.
>From [email protected] Wed Apr 1 02:45:17
>2026
From: Rosen Penev <[email protected]>
Date: Tue, 31 Mar 2026 17:39:05 -0700
Subject: drm/amd/display: Adjust DCE 8-10 clock, don't overclock by 15%
To: [email protected]
Cc: "Alex Deucher" <[email protected]>, "Christian König"
<[email protected]>, "Xinhui Pan" <[email protected]>, "David Airlie"
<[email protected]>, "Simona Vetter" <[email protected]>, "Harry Wentland"
<[email protected]>, "Leo Li" <[email protected]>, "Rodrigo Siqueira"
<[email protected]>, "Ray Wu" <[email protected]>, "Wayne Lin"
<[email protected]>, "Mario Limonciello" <[email protected]>, "Roman
Li" <[email protected]>, "Eric Yang" <[email protected]>, "Tony Cheng"
<[email protected]>, "Mauro Rossi" <[email protected]>, "Timur Kristóf"
<[email protected]>, "Alex Hung" <[email protected]>,
[email protected] (open list:RADEON and AMDGPU DRM DRIVERS),
[email protected] (open list:DRM DRIVERS),
[email protected] (open list)
Message-ID: <[email protected]>
From: Timur Kristóf <[email protected]>
[ Upstream commit 1ae45b5d4f371af8ae51a3827d0ec9fe27eeb867 ]
Adjust the nominal (and performance) clocks for DCE 8-10,
and set them to 625 MHz, which is the value used by the legacy
display code in amdgpu_atombios_get_clock_info.
This was tested with Hawaii, Tonga and Fiji.
These GPUs can output 4K 60Hz (10-bit depth) at 625 MHz.
The extra 15% clock was added as a workaround for a Polaris issue
which uses DCE 11, and should not have been used on DCE 8-10 which
are already hardcoded to the highest possible display clock.
Unfortunately, the extra 15% was mistakenly copied and kept
even on code paths which don't affect Polaris.
This commit fixes that and also adds a check to make sure
not to exceed the maximum DCE 8-10 display clock.
Fixes: 8cd61c313d8b ("drm/amd/display: Raise dispclk value for Polaris")
Fixes: dc88b4a684d2 ("drm/amd/display: make clk mgr soc specific")
Signed-off-by: Timur Kristóf <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Rodrigo Siqueira <[email protected]>
Reviewed-by: Alex Hung <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Rosen Penev <[email protected]>
Signed-off-by: Greg Kroah-Hartman <[email protected]>
---
drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/dce_clk_mgr.c
@@ -72,9 +72,9 @@ static const struct state_dependent_cloc
/* ClocksStateLow */
{ .display_clk_khz = 352000, .pixel_clk_khz = 330000},
/* ClocksStateNominal */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 },
+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 },
/* ClocksStatePerformance */
-{ .display_clk_khz = 600000, .pixel_clk_khz = 400000 } };
+{ .display_clk_khz = 625000, .pixel_clk_khz = 400000 } };
int dentist_get_divider_from_did(int did)
{
@@ -403,11 +403,9 @@ static void dce_update_clocks(struct clk
{
struct clk_mgr_internal *clk_mgr_dce =
TO_CLK_MGR_INTERNAL(clk_mgr_base);
struct dm_pp_power_level_change_request level_change_req;
- int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz;
-
- /*TODO: W/A for dal3 linux, investigate why this works */
- if (!clk_mgr_dce->dfs_bypass_active)
- patched_disp_clk = patched_disp_clk * 115 / 100;
+ const int max_disp_clk =
+
clk_mgr_dce->max_clks_by_state[DM_PP_CLOCKS_STATE_PERFORMANCE].display_clk_khz;
+ int patched_disp_clk = MIN(max_disp_clk,
context->bw_ctx.bw.dce.dispclk_khz);
level_change_req.power_level =
dce_get_required_clocks_state(clk_mgr_base, context);
/* get max clock state from PPLIB */
Patches currently in stable-queue which might be from [email protected] are
queue-6.12/drm-amd-amdgpu-decouple-aspm-with-pcie-dpm.patch
queue-6.12/drm-amd-display-reject-modes-with-too-high-pixel-clock-on-dce6-10.patch
queue-6.12/drm-amd-display-fix-dce-6.0-and-6.4-pll-programming.patch
queue-6.12/drm-amd-display-disable-scaling-on-dce6-for-now.patch
queue-6.12/drm-amd-display-disable-fastboot-on-dce-6-too.patch
queue-6.12/drm-amd-display-correct-logic-check-error-for-fastboot.patch
queue-6.12/drm-amd-amdgpu-disable-aspm-in-some-situations.patch
queue-6.12/drm-amd-display-keep-pll0-running-on-dce-6.0-and-6.4.patch
queue-6.12/drm-amd-display-adjust-dce-8-10-clock-don-t-overclock-by-15.patch
queue-6.12/drm-amd-disable-aspm-on-si.patch
