[PATCH 11/23] drm/amd/display: Disable SYMCLK32_LE root clock gating

[Alex Hung]

From: Sung Joon Kim <sungjoon....@amd.com>

[WHY & HOW]
On display on sequence, enabling SYMCLK32_LE root clock gating
causes issue in link training so disabling it is needed.

Cc: Mario Limonciello <mario.limoncie...@amd.com>
Cc: Alex Deucher <alexander.deuc...@amd.com>
Cc: sta...@vger.kernel.org
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlaus...@amd.com>
Signed-off-by: Sung Joon Kim <sungjoon....@amd.com>
Signed-off-by: Alex Hung <alex.h...@amd.com>
---
 .../gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c 
b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
index 514c6d56925d..da9101b83e8c 100644
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn351/dcn351_resource.c
@@ -736,7 +736,7 @@ static const struct dc_debug_options debug_defaults_drv = {
                        .hdmichar = true,
                        .dpstream = true,
                        .symclk32_se = true,
-                       .symclk32_le = true,
+                       .symclk32_le = false,
                        .symclk_fe = true,
                        .physymclk = false,
                        .dpiasymclk = true,
-- 
2.34.1