> -----Original Message-----
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Xiangliang Yu
> Sent: Tuesday, January 10, 2017 5:01 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Yu, Xiangliang
> Subject: [V2 02/11] drm/amdgpu/gfx8: implement emit_rreg/wreg function
>
> Implement emit_rreg/wreg function for kiq ring.
>
> Signed-off-by: Xiangliang Yu <xiangliang...@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h | 3 ++-
> drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c | 37
> ++++++++++++++++++++++++++++++++
> 2 files changed, 39 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> index 0d821d9..a6524bb 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
> @@ -30,7 +30,8 @@
> #define AMDGPU_PASSTHROUGH_MODE (1 << 3) /* thw whole GPU is
> pass through for VM */
> /* GPU virtualization */
> struct amdgpu_virt {
> - uint32_t caps;
> + uint32_t caps;
> + uint32_t val_offs;
Maybe rename val_offs to register_val_offs to make it clearer what it is used
for. With that change, the patch is:
Reviewed-by: Alex Deucher <alexander.deuc...@amd.com>
> };
>
> #define amdgpu_sriov_enabled(adev) \
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> index b487b97..e619f49 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
> @@ -1373,6 +1373,12 @@ static int gfx_v8_0_kiq_init_ring(struct
> amdgpu_device *adev,
> {
> int r = 0;
>
> + if (amdgpu_sriov_vf(adev)) {
> + r = amdgpu_wb_get(adev, &adev->virt.val_offs);
> + if (r)
> + return r;
> + }
> +
> ring->adev = NULL;
> ring->ring_obj = NULL;
> ring->use_doorbell = true;
> @@ -1399,6 +1405,9 @@ static int gfx_v8_0_kiq_init_ring(struct
> amdgpu_device *adev,
> static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring,
> struct amdgpu_irq_src *irq)
> {
> + if (amdgpu_sriov_vf(ring->adev))
> + amdgpu_wb_free(ring->adev, ring->adev->virt.val_offs);
> +
> amdgpu_ring_fini(ring);
> irq->data = NULL;
> }
> @@ -6681,6 +6690,32 @@ static void gfx_v8_ring_emit_cntxcntl(struct
> amdgpu_ring *ring, uint32_t flags)
> amdgpu_ring_write(ring, 0);
> }
>
> +static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t
> reg)
> +{
> + struct amdgpu_device *adev = ring->adev;
> +
> + amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
> + amdgpu_ring_write(ring, 0 | /* src: register*/
> + (5 << 8) | /* dst: memory */
> + (1 << 20)); /* write confirm */
> + amdgpu_ring_write(ring, reg);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
> + adev->virt.val_offs * 4));
> + amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
> + adev->virt.val_offs * 4));
> +}
> +
> +static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t
> reg,
> + uint32_t val)
> +{
> + amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
> + amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
> + amdgpu_ring_write(ring, reg);
> + amdgpu_ring_write(ring, 0);
> + amdgpu_ring_write(ring, val);
> +}
> +
> static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device
> *adev,
> enum
> amdgpu_interrupt_state state)
> {
> @@ -6995,6 +7030,8 @@ static const struct amdgpu_ring_funcs
> gfx_v8_0_ring_funcs_kiq = {
> .test_ib = gfx_v8_0_ring_test_ib,
> .insert_nop = amdgpu_ring_insert_nop,
> .pad_ib = amdgpu_ring_generic_pad_ib,
> + .emit_rreg = gfx_v8_0_ring_emit_rreg,
> + .emit_wreg = gfx_v8_0_ring_emit_wreg,
> };
>
> static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
> --
> 2.7.4
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
