Implement emit_rreg/wreg function for kiq ring.

Signed-off-by: Xiangliang Yu <xiangliang...@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h |  3 ++-
 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c    | 37 ++++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h 
b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
index 0d821d9..a6524bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_virt.h
@@ -30,7 +30,8 @@
 #define AMDGPU_PASSTHROUGH_MODE        (1 << 3) /* thw whole GPU is pass 
through for VM */
 /* GPU virtualization */
 struct amdgpu_virt {
-       uint32_t caps;
+       uint32_t                caps;
+       uint32_t                val_offs;
 };
 
 #define amdgpu_sriov_enabled(adev) \
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 
b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index b487b97..e619f49 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -1373,6 +1373,12 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device 
*adev,
 {
        int r = 0;
 
+       if (amdgpu_sriov_vf(adev)) {
+               r = amdgpu_wb_get(adev, &adev->virt.val_offs);
+               if (r)
+                       return r;
+       }
+
        ring->adev = NULL;
        ring->ring_obj = NULL;
        ring->use_doorbell = true;
@@ -1399,6 +1405,9 @@ static int gfx_v8_0_kiq_init_ring(struct amdgpu_device 
*adev,
 static void gfx_v8_0_kiq_free_ring(struct amdgpu_ring *ring,
                                   struct amdgpu_irq_src *irq)
 {
+       if (amdgpu_sriov_vf(ring->adev))
+               amdgpu_wb_free(ring->adev, ring->adev->virt.val_offs);
+
        amdgpu_ring_fini(ring);
        irq->data = NULL;
 }
@@ -6681,6 +6690,32 @@ static void gfx_v8_ring_emit_cntxcntl(struct amdgpu_ring 
*ring, uint32_t flags)
        amdgpu_ring_write(ring, 0);
 }
 
+static void gfx_v8_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
+{
+       struct amdgpu_device *adev = ring->adev;
+
+       amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
+       amdgpu_ring_write(ring, 0 |     /* src: register*/
+                               (5 << 8) |      /* dst: memory */
+                               (1 << 20));     /* write confirm */
+       amdgpu_ring_write(ring, reg);
+       amdgpu_ring_write(ring, 0);
+       amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
+                               adev->virt.val_offs * 4));
+       amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
+                               adev->virt.val_offs * 4));
+}
+
+static void gfx_v8_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
+                                 uint32_t val)
+{
+       amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
+       amdgpu_ring_write(ring, (1 << 16)); /* no inc addr */
+       amdgpu_ring_write(ring, reg);
+       amdgpu_ring_write(ring, 0);
+       amdgpu_ring_write(ring, val);
+}
+
 static void gfx_v8_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
                                                 enum amdgpu_interrupt_state 
state)
 {
@@ -6995,6 +7030,8 @@ static const struct amdgpu_ring_funcs 
gfx_v8_0_ring_funcs_kiq = {
        .test_ib = gfx_v8_0_ring_test_ib,
        .insert_nop = amdgpu_ring_insert_nop,
        .pad_ib = amdgpu_ring_generic_pad_ib,
+       .emit_rreg = gfx_v8_0_ring_emit_rreg,
+       .emit_wreg = gfx_v8_0_ring_emit_wreg,
 };
 
 static void gfx_v8_0_set_ring_funcs(struct amdgpu_device *adev)
-- 
2.7.4

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