> as bad as the ARM may be, it can't hold a candle to what the pentium has > become: > 1. RISC CPU (undocumented) in the northbridge (MCH) running ThreadX > 2. RISC CPU in the Ethernet part running ThreadX > 3. Simple CPU in the southbridge (ICH) running, well, who knows. But > the entire system won't come up without that CPU coming up, and the > code for that CPU is (of course!) never going to be available in any > general sense.
the difference is that intel have hidden their µarch changes behind a fixed instruction set. this means that even the bios engineer does not care what µarch the cpu is actually running. i would think that's a feature. i have never heard of threadx in the ethernet part, though i have spent more than my fair share of hours paging through yellow books. (perhaps you're speaking of non-intel parts?) do you have some references? is there some reason you care what the ethernet part is doing to provide a normal register or preboot interface? the southbridge does run some hairy junk. both ahci and ide interfaces require special firmware. i would consider the fact that you can't introspect it to be a feature. the one that you didn't mention is the one that bothers me: smm mode. this has been around for a very long time. smm mode takes a special interrupt and takes over the cpu and runs some real-mode code. things like ps/2 emulation for usb mice and keyboards rely on smm mode. this can really blow up your timing, if you have timing constraints. > can't write code for (1) and (2) because the code in the FLASH has to > be signed with Intel's private key, public version of which is *burned > into the chip in read-only registers*. it's a fine line between hardware and software. or maybe there is no line. - erik
