But random access patterns suck at being speculatively cached.
Linear access patterns still require reasonably careful work for the
caching to do the right thing.
Expecting your entire frame buffer to be cached in L2 isn't particularly
reasonable.
Paul
erik quanstrom wrote:
On Fri Dec 5 14:23:22 EST 2008, [EMAIL PROTECTED] wrote:
Again, you can stream a whole frame buffer reasonably fast - that should
be nearly full-rate; it should be full rate if you pre-fetch with
sufficient advance notice (500-1000 clocks), or DMA. But random access
reads *have* to be slow: you get a stall while the system goes to PCIe
for each cache line you attempt to read from.
Paul
the cpu is allowed to speculatively cache WC memory.
- erik
