>On Jun 27, 2011, at 17:16, Erik Trimble wrote: > >> Think about how things were done with the i386 and i387. That's what I'm= > after. With modern CPU buses like AMD & Intel support, plopping a "co-pro= >cessor" into another CPU socket would really, really help. > >Given the amount of transistors that are available nowadays I think it'd be= > simpler to just create a series of SIMD instructions right in/on general C= >PUs, and skip the whole co-processor angle.
One of the VIA processors was one of the first with specific random and AES instructions. AMD & Intel have followed suite and your can some information here: http://en.wikipedia.org/wiki/AES_instruction_set (Similar instructions have been added for SHA, MD5 (older CPUs), RSA, though typically using building blocks not a single long running instruction) A number of the "crypto accelerators" were much slower than the implementation of a direct implementation in opcodes; one issue, though, what register sets will be used and where will it be saved when the thread is preempted (I'm assuming that the reason why AMD and Intel use different instructions from VIA is possibly because of such details. The current implementation the T3 uses a co-processor (one per core, I think) Casper _______________________________________________ zfs-discuss mailing list zfs-discuss@opensolaris.org http://mail.opensolaris.org/mailman/listinfo/zfs-discuss
