From: Kevin Brace <kevinbr...@bracecomputerlab.com>
Signed-off-by: Kevin Brace <kevinbr...@bracecomputerlab.com>
---
README | 14 +++++++-------
man/sis.man | 5 +++--
src/init.c | 18 +++++++++++-------
src/init301.c | 3 ++-
src/initdef.h | 7 ++++---
src/sis.h | 6 +++---
src/sis_driver.c | 13 +++++++++----
src/sis_setup.c | 6 +++---
src/sis_video.c | 16 ++++++++--------
src/sis_video.h | 6 +++---
src/vgatypes.h | 1 +
11 files changed, 54 insertions(+), 41 deletions(-)
diff --git a/README b/README
index 426bdcc..fabb804 100644
--- a/README
+++ b/README
@@ -31,7 +31,7 @@
o 300 series: SiS 300/305, 540, 630/730
o 315 series: SiS 315/E/PRO, 55x, 650, 651, M650, 740,
- [M]661&[F/M/G]X, [M]741[GX]
+ [M]661&[F/M/G]X, [M]662[MX], [M]741[GX]
o 330 series: SiS 330 ("Xabre"), [M]760[GX], [M]761[GX]
@@ -187,12 +187,12 @@
output, set this option to false.
Option
- (For SiS 650, M650, 651, 661, 741, 760 with either SiS 301LV,
- 302LV or SiS 301C video bridge only) The argument may be "VGA",
- "LCD" or "OFF". Specifying LCD will force the driver to use the
- VGA controller's CRT1 channel for driving the LCD while CRT2 is
- free for TV usage. "OFF" is the same as setting the option
- ForceCRT1 to "false". Default is VGA.
+ (For SiS 650, M650, 651, 661, 662, 741, 760 with either SiS
+ 301LV, 302LV or SiS 301C video bridge only) The argument may
+ be "VGA", "LCD" or "OFF". Specifying LCD will force the driver
+ to use the VGA controller's CRT1 channel for driving the LCD
+ while CRT2 is free for TV usage. "OFF" is the same as setting
+ the option ForceCRT1 to "false". Default is VGA.
Option
Selects the CRT2 output device type. Valid parameters are "LCD",
diff --git a/man/sis.man b/man/sis.man
index 578bb68..6c3294b 100644
--- a/man/sis.man
+++ b/man/sis.man
@@ -29,8 +29,9 @@ driver supports PCI, AGP and PCIe video cards based on the
following chipsets:
.B SiS630/730
.B SiS315/E/H/PRO
.B SiS550/551/552
-.B SiS650/651/661/741
+.B SiS650/651
.B SiS330 (Xabre)
+.B SiS661/662/741
.B SiS760/761
.B XGI Volari V3/V5/V8
.B XGI Volari Z7
@@ -44,7 +45,7 @@ for SiS5597/5598, 530/620 and 6326/AGP/DVD
for SiS300/305, 540 and 630/730
.PP
.B 315/330/340 series
-for SiS315, 55x, 330, 661/741/76x (plus M, FX, MX, GX variants thereof), 340
+for SiS315, 55x, 330, 66x/741/76x (plus M, FX, MX, GX variants thereof), 340
and all XGI chips.
.PP
.SH CONFIGURATION DETAILS
diff --git a/src/init.c b/src/init.c
index 538b662..032489e 100644
--- a/src/init.c
+++ b/src/init.c
@@ -1,7 +1,8 @@
/*
* Mode initializing code (CRT1 section) for
* for SiS 300/305/540/630/730,
- * SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
+ * SiS 315/550/[M]650/651
+ * SiS [M]661[FGM]X/[M]662[MX]/[M]74x[GX]/330/[M]76x[GX],
* XGI Volari V3XT/V5/V8, Z7
* (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
*
@@ -256,7 +257,7 @@ InitTo310Pointer(struct SiS_Private *SiS_Pr)
} else if(SiS_Pr->ChipType >= SIS_760) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_760; /* 760 */
} else if(SiS_Pr->ChipType >= SIS_661) {
- SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_660; /* 661/741 */
+ SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_660; /* 661/662/741 */
} else if(SiS_Pr->ChipType == SIS_330) {
SiS_Pr->SiS_MCLKData_0 = SiS310_MCLKData_0_330; /* 330 */
} else if(SiS_Pr->ChipType > SIS_315PRO) {
@@ -1111,6 +1112,7 @@ SiSInitPCIetc(struct SiS_Private *SiS_Pr)
case SIS_740:
case SIS_330:
case SIS_661:
+ case SIS_662:
case SIS_741:
case SIS_760:
case SIS_761:
@@ -1192,6 +1194,7 @@ SiSSetLVDSetc(struct SiS_Private *SiS_Pr)
if(temp == 3) SiS_Pr->SiS_IF_DEF_CH70xx = 2;
break;
case SIS_661:
+ case SIS_662:
case SIS_741:
case SIS_760:
case SIS_761:
@@ -1255,8 +1258,9 @@ SiSDetermineROMLayout661(struct SiS_Private *SiS_Pr)
if(SiS_Pr->ChipType >= XGI_20) {
/* XGI ROMs don't qualify */
return FALSE;
- } else if(SiS_Pr->ChipType >= SIS_761) {
- /* I very much assume 761, 340 and newer will use new layout */
+ } else if ((SiS_Pr->ChipType >= SIS_761) ||
+ (SiS_Pr->ChipType == SIS_662)) {
+ /* I very much assume 662, 761, 340 and newer will use new layout */
return TRUE;
} else if(SiS_Pr->ChipType >= SIS_661) {
if((ROMAddr[0x1a] == 'N') &&
@@ -1735,7 +1739,7 @@ SiS_OpenCRTC(struct SiS_Private *SiS_Pr)
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
if(IS_SIS651) SiS_SetRegOR(SiS_Pr->SiS_P3d4,0x51,0x20);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
- } else if(IS_SIS661741760761) {
+ } else if(IS_SIS661662741760761) {
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x61,0xf7);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x51,0x1f);
SiS_SetRegAND(SiS_Pr->SiS_P3d4,0x56,0xe7);
@@ -1751,7 +1755,7 @@ SiS_CloseCRTC(struct SiS_Private *SiS_Pr)
#if 0 /* This locks some CRTC registers. We don't want that. */
unsigned short temp1 = 0, temp2 = 0;
- if(IS_SIS661741760761) {
+ if(IS_SIS661662741760761) {
if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCDA) {
temp1 = 0xa0; temp2 = 0x08;
}
@@ -1952,7 +1956,7 @@ SiS_SetATTRegs(struct SiS_Private *SiS_Pr, unsigned short
StandTableIndex)
}
} else if(SiS_Pr->SiS_VBInfo & SetCRT2ToLCD) {
if(SiS_Pr->ChipType >= SIS_315H) {
- if(IS_SIS550650740661741760761) {
+ if(IS_SIS550650740661662741760761) {
/* 315, 330 don't do this */
if(SiS_Pr->SiS_VBType & VB_SIS30xB) {
if(SiS_Pr->SiS_VBInfo & SetInSlaveMode) ARdata = 0;
diff --git a/src/init301.c b/src/init301.c
index e891037..9d487f9 100644
--- a/src/init301.c
+++ b/src/init301.c
@@ -1,7 +1,8 @@
/*
* Mode initializing code (CRT2 section)
* for SiS 300/305/540/630/730,
- * SiS 315/550/[M]650/651/[M]661[FGM]X/[M]74x[GX]/330/[M]76x[GX],
+ * SiS 315/550/[M]650/651
+ * SiS [M]661[FGM]X/[M]662[MX]/[M]74x[GX]/330/[M]76x[GX],
* XGI V3XT/V5/V8, Z7
* (Universal module for Linux kernel framebuffer and X.org/XFree86 4.x)
*
diff --git a/src/initdef.h b/src/initdef.h
index d078024..7e36bbe 100644
--- a/src/initdef.h
+++ b/src/initdef.h
@@ -59,14 +59,15 @@
#define IS_SISM650 (SiS_Pr->SiS_SysFlags & (SF_IsM650 | SF_IsM652
| SF_IsM653))
#define IS_SIS65x (IS_SIS651 || IS_SISM650) /* Only
special versions of 65x */
#define IS_SIS661 (SiS_Pr->ChipType == SIS_661)
+#define IS_SIS662 (SiS_Pr->ChipType == SIS_662)
#define IS_SIS741 (SiS_Pr->ChipType == SIS_741)
#define IS_SIS760 (SiS_Pr->ChipType == SIS_760)
#define IS_SIS761 (SiS_Pr->ChipType == SIS_761)
-#define IS_SIS661741760761 (IS_SIS661 || IS_SIS741 || IS_SIS760 ||
IS_SIS761)
+#define IS_SIS661662741760761 (IS_SIS661 || IS_SIS662 || IS_SIS741 ||
IS_SIS760 || IS_SIS761)
#define IS_SIS650740 ((SiS_Pr->ChipType >= SIS_650) &&
(SiS_Pr->ChipType < SIS_330))
#define IS_SIS550650740 (IS_SIS550 || IS_SIS650740)
-#define IS_SIS650740661741760761 (IS_SIS650 || IS_SIS740 ||
IS_SIS661741760761)
-#define IS_SIS550650740661741760761 (IS_SIS550 || IS_SIS650740661741760761)
+#define IS_SIS650740661662741760761 (IS_SIS650 || IS_SIS740 ||
IS_SIS661662741760761)
+#define IS_SIS550650740661662741760761 (IS_SIS550 ||
IS_SIS650740661662741760761)
#define SISGETROMW(x) (ROMAddr[(x)] | (ROMAddr[(x)+1] << 8))
diff --git a/src/sis.h b/src/sis.h
index bb5ae9c..aa1fe8d 100644
--- a/src/sis.h
+++ b/src/sis.h
@@ -215,7 +215,7 @@
#define SIS_ARGB_CURSOR /* Include code for color hardware
cursors */
-#define ENABLE_YPBPR /* Include YPbPr support on SiS bridges (315
series and 661/741/760) */
+#define ENABLE_YPBPR /* Include YPbPr support on SiS bridges (315
series and 661/662/741/760) */
#define SISVRAMQ /* Use VRAM queue mode on 315/330/340/XGI
series */
@@ -572,7 +572,7 @@ typedef unsigned char UChar;
#define SIS_530_VGA 1
#define SIS_OLD_VGA 2
#define SIS_300_VGA 3
-#define SIS_315_VGA 4 /* Includes 330/661/741/760/761/340 and M versions
thereof, XGI */
+#define SIS_315_VGA 4 /* Includes 330/661/662/741/760/761/340 and M versions
thereof, XGI */
/* pSiS->oldChipset */
#define OC_UNKNOWN 0
@@ -614,7 +614,7 @@ typedef unsigned char UChar;
#define SiSCF_IsXGIDUO SiSCF_IsM652/* Volari Duo */
/* ... */
#define SiSCF_315Core 0x00010000 /* 3D: Real 315 */
-#define SiSCF_Real256ECore 0x00020000 /* 3D: Similar to 315 core, no T&L?
(65x, 661, 740, 741) */
+#define SiSCF_Real256ECore 0x00020000 /* 3D: Similar to 315 core, no T&L?
(65x, 661, 662, 740, 741) */
#define SiSCF_XabreCore 0x00040000 /* 3D: Real Xabre */
#define SiSCF_Ultra256Core 0x00080000 /* 3D: aka "Mirage 2"; similar to
Xabre, no T&L?, no P:Shader? (760) */
#define SiSCF_MMIOPalette 0x00100000 /* HW supports MMIO palette
writing/reading */
diff --git a/src/sis_driver.c b/src/sis_driver.c
index aa25a99..d72086c 100644
--- a/src/sis_driver.c
+++ b/src/sis_driver.c
@@ -188,7 +188,7 @@ static SymTabRec SISChipsets[] = {
{ PCI_CHIP_SIS550, "SIS550" },
{ PCI_CHIP_SIS650, "SIS650/M650/651/740" },
{ PCI_CHIP_SIS330, "SIS330(Xabre)" },
- { PCI_CHIP_SIS660, "SIS[M]661[F|M]X/[M]741[GX]/[M]760[GX]/[M]761[GX]"
},
+ { PCI_CHIP_SIS660,
"SIS[M]661[F|M]X/[M]662[MX]/[M]741[GX]/[M]760[GX]/[M]761[GX]" },
{ PCI_CHIP_SIS340, "SIS340" },
{ -1, NULL }
};
@@ -3422,7 +3422,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
case PCI_CHIP_SIS550:
case PCI_CHIP_SIS650: /* 650 + 740 */
case PCI_CHIP_SIS330:
- case PCI_CHIP_SIS660: /* 661, 741, 760, 761 */
+ case PCI_CHIP_SIS660: /* 661, 662, 741, 760, 761 */
case PCI_CHIP_SIS340:
case PCI_CHIP_XGIXG20:
case PCI_CHIP_XGIXG40:
@@ -3750,7 +3750,7 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->SiS_SD3_Flags |= SiS_SD3_CRT1SATGAIN; /* FIXME ? */
pSiS->myCR63 = 0x53; /* sic! */
break;
- case PCI_CHIP_SIS660: /* 661, 741, 760, 761 */
+ case PCI_CHIP_SIS660: /* 661, 662, 741, 760, 761 */
{
ULong hpciid = sis_pci_read_host_bridge_u32(0x00);
switch(hpciid) {
@@ -3769,10 +3769,14 @@ SISPreInit(ScrnInfoPtr pScrn, int flags)
pSiS->ChipFlags |= SiSCF_Real256ECore;
break;
case 0x06611039:
- default:
pSiS->ChipType = SIS_661;
pSiS->ChipFlags |= SiSCF_Real256ECore;
break;
+ case 0x06621039:
+ default:
+ pSiS->ChipType = SIS_662;
+ pSiS->ChipFlags |= SiSCF_Real256ECore;
+ break;
}
/* Detection could also be done by CR5C & 0xf8:
* 0x10 = 661 (CR5F & 0xc0: 0x00 both A0 and A1)
@@ -12890,6 +12894,7 @@ SiSPostSetMode(ScrnInfoPtr pScrn, SISRegPtr sisReg)
break;
case SIS_661:
+ case SIS_662:
case SIS_741:
clklimit1 = clklimit2 = 190; /* ? */
clklimitg = 180; /* ? */
diff --git a/src/sis_setup.c b/src/sis_setup.c
index 307e68f..ed6e26b 100644
--- a/src/sis_setup.c
+++ b/src/sis_setup.c
@@ -667,7 +667,7 @@ sis315Setup(ScrnInfoPtr pScrn)
pSiS->BusWidth);
}
-/* For 550, 65x, 740, 661, 741, 760, 761 */
+/* For 550, 65x, 740, 661, 662, 741, 760, 761 */
static void
sis550Setup(ScrnInfoPtr pScrn)
{
@@ -743,7 +743,7 @@ sis550Setup(ScrnInfoPtr pScrn)
pSiS->IsPCIExpress = TRUE;
}
- } else { /* 661, 741 */
+ } else { /* 661, 662, 741 */
int dimmnum;
@@ -936,7 +936,7 @@ SiSSetup(ScrnInfoPtr pScrn)
break;
case PCI_CHIP_SIS550:
case PCI_CHIP_SIS650: /* + 740,M650,651 */
- case PCI_CHIP_SIS660: /* + (M)661,(M)741,(M)760(GX), (M)761(GX) */
+ case PCI_CHIP_SIS660: /* + (M)661,(M)662,(M)741,(M)760(GX), (M)761(GX) */
sis550Setup(pScrn);
break;
case PCI_CHIP_SIS5597:
diff --git a/src/sis_video.c b/src/sis_video.c
index 5777ffc..efebbef 100644
--- a/src/sis_video.c
+++ b/src/sis_video.c
@@ -44,14 +44,14 @@
* SiS650/740: Full register range, one overlay (used for both CRT1 and CRT2
alt.)
* SiSM650/651: Full register range, two overlays (one used for CRT1, one for
CRT2)
* SiS330: Full register range, one overlay (used for both CRT1 and CRT2 alt.)
- * SiS661/741/760: Full register range, two overlays (one used for CRT1, one
for CRT2)
+ * SiS661/662/741/760: Full register range, two overlays (one used for CRT1,
one for CRT2)
* SiS340: - ? overlays. Extended registers for DDA.
* SiS761: - ? overlays. Extended registers for DDA.
* XGI Volari V3XT/V5/V8: 1 Overlay. Extended registers for DDA.
*
* Help for reading the code:
- * 315/550/650/740/M650/651/330/661/741/76x/340/XGI = SIS_315_VGA
- * 300/630/730 = SIS_300_VGA
+ * 315/550/650/740/M650/651/330/661/662/741/76x/340/XGI = SIS_315_VGA
+ * 300/630/730 = SIS_300_VGA
* For chipsets with 2 overlays, hasTwoOverlays will be true
*
* Notes on display modes:
@@ -481,7 +481,7 @@ SISResetVideo(ScrnInfoPtr pScrn)
setvideoregmask(pSiS, Index_VI_Key_Overlay_OP, 0x00, 0xE0);
if(pPriv->is760) {
setvideoregmask(pSiS, Index_VI_V_Buf_Start_Over, 0x3c, 0x3c);
- } else { /* 661, 741 */
+ } else { /* 661, 662, 741 */
setvideoregmask(pSiS, Index_VI_V_Buf_Start_Over, 0x2c, 0x3c);
}
} else if((pSiS->Chipset == PCI_CHIP_SIS340) ||
@@ -521,7 +521,7 @@ SISResetVideo(ScrnInfoPtr pScrn)
setvideoreg(pSiS, Index_VI_Win_Ver_Disp_Start_Low, 0x00);
setvideoreg(pSiS, Index_VI_Win_Ver_Over, 0x00);
- /* Initialize second overlay (CRT2) - only for 300, 630/730, 550,
M650/651, 661/741/760/761 */
+ /* Initialize second overlay (CRT2) - only for 300, 630/730, 550,
M650/651, 661/662/741/760/761 */
if(pSiS->hasTwoOverlays) {
if(pSiS->VGAEngine == SIS_300_VGA) {
@@ -560,7 +560,7 @@ SISResetVideo(ScrnInfoPtr pScrn)
CARD8 temp;
setvideoregmask(pSiS, Index_VI_Key_Overlay_OP, 0x00, 0xE0);
switch(pSiS->ChipType) {
- case SIS_661: temp = 0x24; break;
+ case SIS_661: case SIS_662: temp = 0x24; break;
case SIS_741: temp = 0x2c; break;
default: temp = 0x3c;
}
@@ -1077,7 +1077,7 @@ SISSetupImageVideo(ScreenPtr pScreen)
* 650/740 2 960 ("120x128") 1920x1080
* M650/651.. 4 480 1920x1080
* 330 2 960 1920x1080
- * 661/741/760 4 768 1920x1080
+ * 66x/741/760 4 768 1920x1080
* 340 4 1280? 1920x1080?
* 761 4 1536? 1920x1080?
* The unit of size is unknown; I just know that a size of 480 limits
@@ -1089,7 +1089,7 @@ SISSetupImageVideo(ScreenPtr pScreen)
* either only CRT1 or only CRT2 is used.
* If both overlays are going to be used (such as in modes were both
* CRT1 and CRT2 are active), we are limited to the half of the
- * maximum width, or 1536 on 661/741/760.
+ * maximum width, or 1536 on 66x/741/760.
* There is a known hardware problem with the 760 and 761 if the video
* data is in the UMA area: The memory access latency is too big to
* allow two overlays under some circumstances. Therefore, we must
diff --git a/src/sis_video.h b/src/sis_video.h
index c722799..d57f31e 100644
--- a/src/sis_video.h
+++ b/src/sis_video.h
@@ -44,14 +44,14 @@
* SiS650/740: Full register range, one overlay (used for both CRT1 and CRT2
alt.)
* SiSM650/651: Full register range, two overlays (one used for CRT1, one for
CRT2)
* SiS330: Full register range, one overlay (used for both CRT1 and CRT2 alt.)
- * SiS661/741/760: Full register range, two overlays (one used for CRT1, one
for CRT2)
+ * SiS661/662/741/760: Full register range, two overlays (one used for CRT1,
one for CRT2)
* SiS340: - ? overlay(s)? Extended registers for DDA?
* SiS761: - ? overlay(s)? Extended registers for DDA.
* XGI V5/V8/Z7 - 1 overlay, extended registers for DDA.
*
* Help for reading the code:
- * 315/550/650/740/M650/651/330/661/741/76x/340/XGI = SIS_315_VGA
- * 300/630/730 = SIS_300_VGA
+ * 315/550/650/740/M650/651/330/661/662/741/76x/340/XGI = SIS_315_VGA
+ * 300/630/730 = SIS_300_VGA
* For chipsets with 2 overlays, hasTwoOverlays will be true
*
* Notes on display modes:
diff --git a/src/vgatypes.h b/src/vgatypes.h
index 02a012f..a7c125e 100644
--- a/src/vgatypes.h
+++ b/src/vgatypes.h
@@ -95,6 +95,7 @@ typedef enum _SIS_CHIP_TYPE {
SIS_740,
SIS_330,
SIS_661,
+ SIS_662,
SIS_741,
SIS_760 = 35,
SIS_761,
--
2.17.1
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