On 19/04/2021 17:00, Jan Beulich wrote: > On 19.04.2021 17:57, Andrew Cooper wrote: >> On 19/04/2021 16:55, Jan Beulich wrote: >>> On 19.04.2021 16:45, Andrew Cooper wrote: >>>> Factor out a compat boolean to remove the lfence overhead from multiple >>>> is_pv_32bit_domain() calls. >>>> >>>> For a compat guest, the upper 32 bits of rdx are zero, so there is no need >>>> to >>>> have any conditional logic at all when mapping the start info page. >>> Iirc the contents of the upper halves hold unspecified contents after >>> a switch from compat to 64-bit mode. Therefore only with this part of >>> the change dropped ... >> But we're shim, so will never ever mix compat and non-compat guests. > That's not the point: A compat guest will still cause the CPU to > transition back and forth between 64-bit and compat modes. It is > this transitioning which leaves the upper halves of all GPRs in > undefined state (even if in reality a CPU would likely need to go > through extra hoops to prevent them from being zero if they were > written to in compat mode).
Hmm. That's awkward. So real behaviour (I've checked with some contacts) is that upper bits are preserved until the next write to the register, after which the upper bits are zeroed. I wonder whether I'll have any luck formally asking AMD and Intel for a tweak to this effect in the manuals. ~Andrew
