On 12.04.2021 17:06, Andrew Cooper wrote: > While part of the original AMD64 spec, Long Mode Segment Limit was a feature > not picked up by Intel, and therefore didn't see much adoption in software. > AMD have finally dropped the feature from hardware, and allocated a CPUID bit > to indicate its absence. > > Xen has never supported the feature for guests, even when running on capable > hardware, so advertise the feature's absence unilaterally. > > There is nothing specifically wrong with exposing this bit to PV guests, but > the PV ABI doesn't include a working concept of MSR_EFER in the first place, > so exposing it to PV guests would be out-of-place. > > Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
