Hi Volodymyr,
> On 30 Nov 2020, at 20:22, Volodymyr Babchuk <volodymyr_babc...@epam.com>
> wrote:
>
>
>
> Bertrand Marquis writes:
>
>> Add vsysreg emulation for registers trapped when TID3 bit is activated
>> in HSR.
>> The emulation is returning the value stored in cpuinfo_guest structure
>> for most values and the hardware value for registers not stored in the
>> structure (those are mostly registers existing only as a provision for
>> feature use but who have no definition right now).
>
> I can't see the code that returns values for the registers not stored in
> the guest_cpuinfo. Perhaps you need to update the commit description?
You are right, i modified my code lately to handle all possible registers so
this case does not exist anymore.
I will update the commit message to fix this.
Cheers
Bertrand
>
>> Signed-off-by: Bertrand Marquis <bertrand.marq...@arm.com>
>> ---
>> Changes in V2: rebase
>> ---
>> xen/arch/arm/arm64/vsysreg.c | 49 ++++++++++++++++++++++++++++++++++++
>> 1 file changed, 49 insertions(+)
>>
>> diff --git a/xen/arch/arm/arm64/vsysreg.c b/xen/arch/arm/arm64/vsysreg.c
>> index 8a85507d9d..970ef51603 100644
>> --- a/xen/arch/arm/arm64/vsysreg.c
>> +++ b/xen/arch/arm/arm64/vsysreg.c
>> @@ -69,6 +69,14 @@ TVM_REG(CONTEXTIDR_EL1)
>> break; \
>> }
>>
>> +/* Macro to generate easily case for ID co-processor emulation */
>> +#define GENERATE_TID3_INFO(reg,field,offset) \
>> + case HSR_SYSREG_##reg: \
>> + { \
>> + return handle_ro_read_val(regs, regidx, hsr.sysreg.read, hsr, \
>> + 1, guest_cpuinfo.field.bits[offset]); \
>> + }
>> +
>> void do_sysreg(struct cpu_user_regs *regs,
>> const union hsr hsr)
>> {
>> @@ -259,6 +267,47 @@ void do_sysreg(struct cpu_user_regs *regs,
>> */
>> return handle_raz_wi(regs, regidx, hsr.sysreg.read, hsr, 1);
>>
>> + /*
>> + * HCR_EL2.TID3
>> + *
>> + * This is trapping most Identification registers used by a guest
>> + * to identify the processor features
>> + */
>> + GENERATE_TID3_INFO(ID_PFR0_EL1, pfr32, 0)
>> + GENERATE_TID3_INFO(ID_PFR1_EL1, pfr32, 1)
>> + GENERATE_TID3_INFO(ID_PFR2_EL1, pfr32, 2)
>> + GENERATE_TID3_INFO(ID_DFR0_EL1, dbg32, 0)
>> + GENERATE_TID3_INFO(ID_DFR1_EL1, dbg32, 1)
>> + GENERATE_TID3_INFO(ID_AFR0_EL1, aux32, 0)
>> + GENERATE_TID3_INFO(ID_MMFR0_EL1, mm32, 0)
>> + GENERATE_TID3_INFO(ID_MMFR1_EL1, mm32, 1)
>> + GENERATE_TID3_INFO(ID_MMFR2_EL1, mm32, 2)
>> + GENERATE_TID3_INFO(ID_MMFR3_EL1, mm32, 3)
>> + GENERATE_TID3_INFO(ID_MMFR4_EL1, mm32, 4)
>> + GENERATE_TID3_INFO(ID_MMFR5_EL1, mm32, 5)
>> + GENERATE_TID3_INFO(ID_ISAR0_EL1, isa32, 0)
>> + GENERATE_TID3_INFO(ID_ISAR1_EL1, isa32, 1)
>> + GENERATE_TID3_INFO(ID_ISAR2_EL1, isa32, 2)
>> + GENERATE_TID3_INFO(ID_ISAR3_EL1, isa32, 3)
>> + GENERATE_TID3_INFO(ID_ISAR4_EL1, isa32, 4)
>> + GENERATE_TID3_INFO(ID_ISAR5_EL1, isa32, 5)
>> + GENERATE_TID3_INFO(ID_ISAR6_EL1, isa32, 6)
>> + GENERATE_TID3_INFO(MVFR0_EL1, mvfr, 0)
>> + GENERATE_TID3_INFO(MVFR1_EL1, mvfr, 1)
>> + GENERATE_TID3_INFO(MVFR2_EL1, mvfr, 2)
>> + GENERATE_TID3_INFO(ID_AA64PFR0_EL1, pfr64, 0)
>> + GENERATE_TID3_INFO(ID_AA64PFR1_EL1, pfr64, 1)
>> + GENERATE_TID3_INFO(ID_AA64DFR0_EL1, dbg64, 0)
>> + GENERATE_TID3_INFO(ID_AA64DFR1_EL1, dbg64, 1)
>> + GENERATE_TID3_INFO(ID_AA64ISAR0_EL1, isa64, 0)
>> + GENERATE_TID3_INFO(ID_AA64ISAR1_EL1, isa64, 1)
>> + GENERATE_TID3_INFO(ID_AA64MMFR0_EL1, mm64, 0)
>> + GENERATE_TID3_INFO(ID_AA64MMFR1_EL1, mm64, 1)
>> + GENERATE_TID3_INFO(ID_AA64MMFR2_EL1, mm64, 2)
>> + GENERATE_TID3_INFO(ID_AA64AFR0_EL1, aux64, 0)
>> + GENERATE_TID3_INFO(ID_AA64AFR1_EL1, aux64, 1)
>> + GENERATE_TID3_INFO(ID_AA64ZFR0_EL1, zfr64, 0)
>> +
>> /*
>> * HCR_EL2.TIDCP
>> *
>
>
> --
> Volodymyr Babchuk at EPAM
