Bertrand Marquis writes:
> Add coprocessor registers definitions for all ID registers trapped > through the TID3 bit of HSR. > Those are the one that will be emulated in Xen to only publish to guests > the features that are supported by Xen and that are accessible to > guests. > > Signed-off-by: Bertrand Marquis <bertrand.marq...@arm.com> Reviewed-by: Volodymyr Babchuk <volodymyr_babc...@epam.com> > --- > Changes in V2: rebase > --- > xen/include/asm-arm/arm64/hsr.h | 37 +++++++++++++++++++++++++++++++++ > 1 file changed, 37 insertions(+) > > diff --git a/xen/include/asm-arm/arm64/hsr.h b/xen/include/asm-arm/arm64/hsr.h > index ca931dd2fe..e691d41c17 100644 > --- a/xen/include/asm-arm/arm64/hsr.h > +++ b/xen/include/asm-arm/arm64/hsr.h > @@ -110,6 +110,43 @@ > #define HSR_SYSREG_CNTP_CTL_EL0 HSR_SYSREG(3,3,c14,c2,1) > #define HSR_SYSREG_CNTP_CVAL_EL0 HSR_SYSREG(3,3,c14,c2,2) > > +/* Those registers are used when HCR_EL2.TID3 is set */ > +#define HSR_SYSREG_ID_PFR0_EL1 HSR_SYSREG(3,0,c0,c1,0) > +#define HSR_SYSREG_ID_PFR1_EL1 HSR_SYSREG(3,0,c0,c1,1) > +#define HSR_SYSREG_ID_PFR2_EL1 HSR_SYSREG(3,0,c0,c3,4) > +#define HSR_SYSREG_ID_DFR0_EL1 HSR_SYSREG(3,0,c0,c1,2) > +#define HSR_SYSREG_ID_DFR1_EL1 HSR_SYSREG(3,0,c0,c3,5) > +#define HSR_SYSREG_ID_AFR0_EL1 HSR_SYSREG(3,0,c0,c1,3) > +#define HSR_SYSREG_ID_MMFR0_EL1 HSR_SYSREG(3,0,c0,c1,4) > +#define HSR_SYSREG_ID_MMFR1_EL1 HSR_SYSREG(3,0,c0,c1,5) > +#define HSR_SYSREG_ID_MMFR2_EL1 HSR_SYSREG(3,0,c0,c1,6) > +#define HSR_SYSREG_ID_MMFR3_EL1 HSR_SYSREG(3,0,c0,c1,7) > +#define HSR_SYSREG_ID_MMFR4_EL1 HSR_SYSREG(3,0,c0,c2,6) > +#define HSR_SYSREG_ID_MMFR5_EL1 HSR_SYSREG(3,0,c0,c3,6) > +#define HSR_SYSREG_ID_ISAR0_EL1 HSR_SYSREG(3,0,c0,c2,0) > +#define HSR_SYSREG_ID_ISAR1_EL1 HSR_SYSREG(3,0,c0,c2,1) > +#define HSR_SYSREG_ID_ISAR2_EL1 HSR_SYSREG(3,0,c0,c2,2) > +#define HSR_SYSREG_ID_ISAR3_EL1 HSR_SYSREG(3,0,c0,c2,3) > +#define HSR_SYSREG_ID_ISAR4_EL1 HSR_SYSREG(3,0,c0,c2,4) > +#define HSR_SYSREG_ID_ISAR5_EL1 HSR_SYSREG(3,0,c0,c2,5) > +#define HSR_SYSREG_ID_ISAR6_EL1 HSR_SYSREG(3,0,c0,c2,7) > +#define HSR_SYSREG_MVFR0_EL1 HSR_SYSREG(3,0,c0,c3,0) > +#define HSR_SYSREG_MVFR1_EL1 HSR_SYSREG(3,0,c0,c3,1) > +#define HSR_SYSREG_MVFR2_EL1 HSR_SYSREG(3,0,c0,c3,2) > + > +#define HSR_SYSREG_ID_AA64PFR0_EL1 HSR_SYSREG(3,0,c0,c4,0) > +#define HSR_SYSREG_ID_AA64PFR1_EL1 HSR_SYSREG(3,0,c0,c4,1) > +#define HSR_SYSREG_ID_AA64DFR0_EL1 HSR_SYSREG(3,0,c0,c5,0) > +#define HSR_SYSREG_ID_AA64DFR1_EL1 HSR_SYSREG(3,0,c0,c5,1) > +#define HSR_SYSREG_ID_AA64ISAR0_EL1 HSR_SYSREG(3,0,c0,c6,0) > +#define HSR_SYSREG_ID_AA64ISAR1_EL1 HSR_SYSREG(3,0,c0,c6,1) > +#define HSR_SYSREG_ID_AA64MMFR0_EL1 HSR_SYSREG(3,0,c0,c7,0) > +#define HSR_SYSREG_ID_AA64MMFR1_EL1 HSR_SYSREG(3,0,c0,c7,1) > +#define HSR_SYSREG_ID_AA64MMFR2_EL1 HSR_SYSREG(3,0,c0,c7,2) > +#define HSR_SYSREG_ID_AA64AFR0_EL1 HSR_SYSREG(3,0,c0,c5,4) > +#define HSR_SYSREG_ID_AA64AFR1_EL1 HSR_SYSREG(3,0,c0,c5,5) > +#define HSR_SYSREG_ID_AA64ZFR0_EL1 HSR_SYSREG(3,0,c0,c4,4) > + > #endif /* __ASM_ARM_ARM64_HSR_H */ > > /* -- Volodymyr Babchuk at EPAM
