> On 25 Nov 2020, at 11:26, Julien Grall <jul...@xen.org> wrote:
>
>
>
> On 24/11/2020 17:44, Stefano Stabellini wrote:
>> On Tue, 24 Nov 2020, Rahul Singh wrote:
>>>> On 24 Nov 2020, at 11:12 am, Bertrand Marquis <bertrand.marq...@arm.com>
>>>> wrote:
>>>>
>>>> On the Cortex A55, TLB entries can be allocated by a speculative AT
>>>> instruction. If this is happening during a guest context switch with an
>>>> inconsistent page table state in the guest, TLBs with wrong values might
>>>> be allocated.
>>>> The ARM64_WORKAROUND_AT_SPECULATE workaround is used as for erratum
>>>> 1165522 on Cortex A76 or Neoverse N1.
>>>>
>>>> This change is also introducing the MIDR identifier for the Cortex-A55.
>>>>
>>>> Signed-off-by: Bertrand Marquis <bertrand.marq...@arm.com>
>>>
>>> Reviewed-by: Rahul Singh <rahul.si...@arm.com>
>> Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
>
> Acked-by: Julien Grall <jgr...@amazon.com>
>
> And committed.
Thanks :-)
Cheers
Bertrand
>
> Cheers,
>
> --
> Julien Grall
