Hi,
> On 23 Sep 2020, at 09:28, Julien Grall <jul...@xen.org> wrote:
>
> From: Julien Grall <jgr...@amazon.com>
>
> SMMUv{1, 2} are both marked as security supported, so we would
> technically have to issue an XSA for any IOMMU security bug.
>
> However, at the moment, device passthrough is not security supported
> on Arm and there is no plan to change that in the next few months.
>
> Therefore, mark Arm SMMUv{1, 2} as supported but not security supported.
>
> Signed-off-by: Julien Grall <jgr...@amazon.com>
Reviewed-by: Bertrand Marquis <bertrand.marq...@arm.com>
We will publish in the next week a first implementation of SMMUv3 support which
might make sense to have fully Supported.
Cheers,
Bertrand
>
> ---
>
> Cc: Bertrand Marquis <bertrand.marq...@arm.com>
> ---
> SUPPORT.md | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/SUPPORT.md b/SUPPORT.md
> index 25987ec1dfb6..f35943a432f7 100644
> --- a/SUPPORT.md
> +++ b/SUPPORT.md
> @@ -62,8 +62,8 @@ supported in this document.
>
> Status, AMD IOMMU: Supported
> Status, Intel VT-d: Supported
> - Status, ARM SMMUv1: Supported
> - Status, ARM SMMUv2: Supported
> + Status, ARM SMMUv1: Supported, not security supported
> + Status, ARM SMMUv2: Supported, not security supported
> Status, Renesas IPMMU-VMSA: Supported, not security supported
>
> ### ARM/GICv3 ITS
> --
> 2.17.1
>
