We already have special casing to handle reads of this MSR for revF chips, so do as the comment in svm_msr_read_intercept says and drop writes. This is in preparation for changing the default MSR write behavior, which will instead return #GP on not explicitly handled writes.
Signed-off-by: Roger Pau Monné <roger....@citrix.com> --- Changes since v1: - New in this version. --- xen/arch/x86/hvm/svm/svm.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/xen/arch/x86/hvm/svm/svm.c b/xen/arch/x86/hvm/svm/svm.c index 2d0823e7e1..7586b77268 100644 --- a/xen/arch/x86/hvm/svm/svm.c +++ b/xen/arch/x86/hvm/svm/svm.c @@ -2125,6 +2125,12 @@ static int svm_msr_write_intercept(unsigned int msr, uint64_t msr_content) nsvm->ns_msr_hsavepa = msr_content; break; + case MSR_F10_BU_CFG: + /* See comment in svm_msr_read_intercept. */ + if ( boot_cpu_data.x86 != 0xf ) + goto gpf; + break; + case MSR_AMD64_TSC_RATIO: if ( msr_content & TSC_RATIO_RSVD_BITS ) goto gpf; -- 2.28.0