On 07.07.2020 21:39, Michał Leszczyński wrote: > --- a/xen/arch/x86/hvm/vmx/vmcs.c > +++ b/xen/arch/x86/hvm/vmx/vmcs.c > @@ -291,6 +291,20 @@ static int vmx_init_vmcs_config(void) > _vmx_cpu_based_exec_control &= > ~(CPU_BASED_CR8_LOAD_EXITING | CPU_BASED_CR8_STORE_EXITING); > > + rdmsrl(MSR_IA32_VMX_MISC, _vmx_misc_cap); > + > + /* Check whether IPT is supported in VMX operation. */ > + if ( !smp_processor_id() )
Despite us not supporting offlining and re-onlining of the BSP (i.e. CPU 0) yet, I'm trying hard to keep new code from making assumptions like this one. Please don't base this on CPU number, but some other property (system_state, if nothing else can be found). Jan
