----- 16 cze 2020 o 19:38, Roger Pau Monné roger....@citrix.com napisał(a):
> On Tue, Jun 16, 2020 at 05:24:11PM +0200, Michał Leszczyński wrote: >> Enable IPT when entering the VM and disable it on vmexit. >> Register state is persisted using vCPU ipt_state structure. > > Shouldn't this be better done using Intel MSR load lists? > > That seems to be what the SDM recommends for tracing VM events. > > Thanks, Roger. This is intentional, additionally described by the comment: // MSR_IA32_RTIT_CTL is context-switched manually instead of being // stored inside VMCS, as of Q2'20 only the most recent processors // support such field in VMCS There is a special feature flag which indicates whether MSR_IA32_RTIT_CTL can be loaded using MR load lists. During my experiments, I haven't found any single CPU available to me that would declare such a feature flag. I was mostly testing CPUs that were launched in 2018, so I suppose that this feature is present only on very recent hardware. Unfortunately it's not possible to check on Intel ARK as this information is not listed there at all. Best regards, Michał Leszczyński CERT Polska
