On 25.05.2020 19:30, Andrew Cooper wrote: > On 25/05/2020 16:23, Jan Beulich wrote: >> On 25.05.2020 17:18, Jan Beulich wrote: >>> Linux commit f8edbde885bbcab6a2b4a1b5ca614e6ccb807577 says >>> >>> "Coffee Lake H SoC has similar behavior as Coffee Lake, skewed HPET >>> timer once the SoCs entered PC10." >>> >>> Again follow this for Xen as well, noting though that even the >>> pre-existing PCI ID refers to a H-processor line variant (the 6-core >>> one). It is also suspicious that the datasheet names 0x3e10 for the >>> 4-core variant, while the Linux commit specifies 0x3e20, which I haven't >>> been able to locate in any datasheet yet. > > 3e20 is the host bridge ID for CFL-R (Gen 9) Core i9 (8c/16t) as found > in the Dell XPS 15 7590 amongst other things. > > As such, it is a generation later than CFL.
Ah, and I should have checked again before submitting - the pretty new rev 003 datasheet actually includes all three IDs now. I've adjusted description and code comments accordingly. >>> To be on the safe side, add >>> both until clarification can be provided by Intel. >>> >>> Signed-off-by: Jan Beulich <jbeul...@suse.com> > > Given the nature of issue (a power efficiently "feature" rather than a > bug), it will likely affect everything in a couple of generations worth > of CPUs. > > The issue may not actually affect Xen yet, because I don't expect we've > got S0ix working yet. It is only a problem on entry to S0i2/3 where the > HPET is halted. While looking into this a while ago I cam across this as well, but I couldn't deduce whether entering PC10 is indeed possible _only_ this way. Jan
