This bug was first discovered against Haswell. It is definitely affected.
(The XenServer ticket for this bug was opened on 2013-05-30 which is coming up
on 7 years old, and predates Broadwell).
Signed-off-by: Andrew Cooper <andrew.coop...@citrix.com>
---
CC: Jan Beulich <jbeul...@suse.com>
CC: Wei Liu <w...@xen.org>
CC: Roger Pau Monné <roger....@citrix.com>
We've followed up with Intel, but based on conversations, I was expecting
Haswell to be treated the same as Broadwell in this regard.
---
xen/arch/x86/acpi/cpu_idle.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/xen/arch/x86/acpi/cpu_idle.c b/xen/arch/x86/acpi/cpu_idle.c
index 178cb607c2..a2248ea11f 100644
--- a/xen/arch/x86/acpi/cpu_idle.c
+++ b/xen/arch/x86/acpi/cpu_idle.c
@@ -583,8 +583,16 @@ bool errata_c6_workaround(void)
* registers), the processor may dispatch the second interrupt (from
* the IRR bit) before the first interrupt has completed and written to
* the EOI register, causing the first interrupt to never complete.
+ *
+ * Note: Haswell hasn't had errata issued, but this issue was first
+ * discovered on Haswell hardware, and is affected.
*/
static const struct x86_cpu_id isr_errata[] = {
+ /* Haswell */
+ INTEL_FAM6_MODEL(0x3c),
+ INTEL_FAM6_MODEL(0x3f),
+ INTEL_FAM6_MODEL(0x45),
+ INTEL_FAM6_MODEL(0x46),
/* Broadwell */
INTEL_FAM6_MODEL(0x47),
INTEL_FAM6_MODEL(0x3d),
--
2.11.0
