qHi Stefano, On 27/03/2020 02:34, Stefano Stabellini wrote:
This is a simple implementation of GICD_ICACTIVER / GICD_ISACTIVER reads. It doesn't take into account the latest state of interrupts on other vCPUs. Only the current vCPU is up-to-date. A full solution is not possible because it would require synchronization among all vCPUs, which would be very expensive in terms or latency.
Your sentence suggests you have number showing that correctly emulating the registers would be too slow. Mind sharing them?
Cheers, -- Julien Grall
