On 02/03/2020 14:07, Jan Beulich wrote: > From: Tony Luck <[email protected]> > > There are two implemented bits in the PPIN_CTL MSR: > > Bit0: LockOut (R/WO) > Set 1 to prevent further writes to MSR_PPIN_CTL. > > Bit 1: Enable_PPIN (R/W) > If 1, enables MSR_PPIN to be accessible using RDMSR. > If 0, an attempt to read MSR_PPIN will cause #GP. > > So there are four defined values: > 0: PPIN is disabled, PPIN_CTL may be updated > 1: PPIN is disabled. PPIN_CTL is locked against updates > 2: PPIN is enabled. PPIN_CTL may be updated > 3: PPIN is enabled. PPIN_CTL is locked against updates > > Code would only enable the X86_FEATURE_INTEL_PPIN feature for case "2". > When it should have done so for both case "2" and case "3". > > Fix the final test to just check for the enable bit. > Also fix some of the other comments in this function. > > Signed-off-by: Tony Luck <[email protected]> > [Linux commit ???] > > One of the adjusted comments doesn't exist in our code, and I disagree > with the adjustment to the other one and its associate code change: I > don't think there's a point trying to enable PPIN if the locked bit is > set. Hence it's just the main code change that gets pulled in, plus it > gets cloned to the AMD side. > > Requested-by: Andrew Cooper <[email protected]> > Signed-off-by: Jan Beulich <[email protected]>
I agree. If it is locked, there is no point trying to change it. Reviewed-by: Andrew Cooper <[email protected]> _______________________________________________ Xen-devel mailing list [email protected] https://lists.xenproject.org/mailman/listinfo/xen-devel
