On 26.11.2019 14:26, Roger Pau Monne wrote:
> --- a/xen/arch/x86/hvm/vmx/vmx.c
> +++ b/xen/arch/x86/hvm/vmx/vmx.c
> @@ -2054,6 +2054,19 @@ static void vmx_sync_pir_to_irr(struct vcpu *v)
> unsigned int group, i;
> DECLARE_BITMAP(pending_intr, NR_VECTORS);
>
> + if ( v != current && !atomic_read(&v->pause_count) )
> + {
> + /*
> + * Syncing PIR to IRR must not be done behind the back of the CPU,
> + * since the IRR is controlled by the hardware when the vCPU is
> + * executing. Only allow Xen to do such sync if the vCPU is the
> current
> + * one or if it's paused: that's required in order to sync the lapic
> + * state before saving it.
> + */
Is this stated this way by the SDM anywhere? I ask because the
comment then really doesn't apply to just this function, but to
vlapic_{,test_and_}{set,clear}_vector() more generally. It's
not clear to me at all whether the CPU caches (in an incoherent
fashion) IRR (and maybe other APIC page elements), rather than
honoring the atomic updates these macros do.
Jan
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