On 22.11.2019 13:58, Andrew Cooper wrote:
On 22/11/2019 12:57, Jan Beulich wrote:
On 22.11.2019 13:50, Andrew Cooper wrote:
On 22/11/2019 12:46, Jan Beulich wrote:
Linux commit fc5db58539b49351e76f19817ed1102bf7c712d0 says
"Some Coffee Lake platforms have a skewed HPET timer once the SoCs entered
PC10, which in consequence marks TSC as unstable because HPET is used as
watchdog clocksource for TSC."
Adjust a few types in touched or nearby code at the same time.
Reported-by ?
The Linux commit has a Suggested-by, but no Reported-by. Do you
want me to copy that one? Or else do you have any suggestion as
to who the reporter was?
Well - this patch was identified by someone on xen-devel, which I
presume was your basis for looking into it.
https://lists.xenproject.org/archives/html/xen-devel/2019-11/msg00662.html
BTW: Xeon E-2136 @ C242 has 8086:3eca as ID. One needs to check with
Intel which combinations are really affected.
Regards Andreas
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