On 23.10.2019 10:57, Roger Pau Monne wrote:
> If a HVM/PVH guest writes to MSR_IA32_TSC{_ADJUST} and thus changes
> the value of the time stamp counter the vcpu time info must also be
> updated, or the time calculated by the guest using the Xen PV clock
> interface will be skewed.
>
> Update the vcpu time info when the guest writes to either MSR_IA32_TSC
> or MSR_IA32_TSC_ADJUST. This fixes lockups seen when running the
> pv-shim on AMD hardware, since the shim will aggressively try to keep
> TSCs in sync by periodically writing to MSR_IA32_TSC if the TSC is not
> reliable.
>
> Signed-off-by: Roger Pau Monné <roger....@citrix.com>
Reviewed-by: Jan Beulich <jbeul...@suse.com>
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