This allows in particular some streamlining of the TLB flushing code
paths.
Signed-off-by: Jan Beulich <jbeul...@suse.com>
---
v2: Avoid #ifdef in cr3_pcid().
--- a/xen/arch/x86/flushtlb.c
+++ b/xen/arch/x86/flushtlb.c
@@ -24,6 +24,11 @@
#define WRAP_MASK (0x000003FFU)
#endif
+#ifndef CONFIG_PV
+# undef X86_CR4_PCIDE
+# define X86_CR4_PCIDE 0
+#endif
+
u32 tlbflush_clock = 1U;
DEFINE_PER_CPU(u32, tlbflush_time);
--- a/xen/include/asm-x86/processor.h
+++ b/xen/include/asm-x86/processor.h
@@ -289,7 +289,7 @@ static inline unsigned long cr3_pa(unsig
static inline unsigned int cr3_pcid(unsigned long cr3)
{
- return cr3 & X86_CR3_PCID_MASK;
+ return IS_ENABLED(CONFIG_PV) ? cr3 & X86_CR3_PCID_MASK : 0;
}
static inline unsigned long read_cr4(void)
@@ -301,8 +301,12 @@ static inline void write_cr4(unsigned lo
{
struct cpu_info *info = get_cpu_info();
+#ifdef CONFIG_PV
/* No global pages in case of PCIDs enabled! */
ASSERT(!(val & X86_CR4_PGE) || !(val & X86_CR4_PCIDE));
+#else
+ ASSERT(!(val & X86_CR4_PCIDE));
+#endif
/*
* On hardware supporting FSGSBASE, the value in %cr4 is the kernel's
--- a/xen/include/asm-x86/pv/domain.h
+++ b/xen/include/asm-x86/pv/domain.h
@@ -50,8 +50,13 @@
*/
static inline unsigned long get_pcid_bits(const struct vcpu *v, bool is_xpti)
{
+#ifdef CONFIG_PV
return X86_CR3_NOFLUSH | (is_xpti ? PCID_PV_XPTI : 0) |
((v->arch.flags & TF_kernel_mode) ? PCID_PV_PRIV : PCID_PV_USER);
+#else
+ ASSERT_UNREACHABLE();
+ return 0;
+#endif
}
#ifdef CONFIG_PV
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