On Mon, 22 Jul 2019, Julien Grall wrote:
> Document the behavior and the main registers usage within enable_mmu().
>
> Signed-off-by: Julien Grall <julien.gr...@arm.com>
Reviewed-by: Stefano Stabellini <sstabell...@kernel.org>
> ---
> Changes in v2:
> - x2 and x3 are also clobbers. Update the comment accordingly
> - s/ID/1:1/
> ---
> xen/arch/arm/arm64/head.S | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/xen/arch/arm/arm64/head.S b/xen/arch/arm/arm64/head.S
> index eddf663021..63563ef5e3 100644
> --- a/xen/arch/arm/arm64/head.S
> +++ b/xen/arch/arm/arm64/head.S
> @@ -576,6 +576,13 @@ virtphys_clash:
> ret
> ENDPROC(create_page_tables)
>
> +/*
> + * Turn on the Data Cache and the MMU. The function will return on the 1:1
> + * mapping. In other word, the caller is responsible to switch to the runtime
> + * mapping.
> + *
> + * Clobbers x0 - x3
> + */
> enable_mmu:
> PRINT("- Turning on paging -\r\n")
>
> --
> 2.11.0
>
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