On 04/07/2019 15:50, Jan Beulich wrote:
> On 04.07.2019 16:44, Andrew Cooper wrote:
>> On 01/07/2019 12:20, Jan Beulich wrote:
>>> + /* Clear untouched parts of the mask value. */
>>> + n = 1 << (4 - ((b & 1) | evex.w));
>>> + op_mask &= (1 << n) - 1;
>>> +
>>> + for ( i = 0; rc == X86EMUL_OKAY && op_mask; ++i )
>>> + {
>>> + signed long idx = b & 1 ? index.qw[i] : index.dw[i];
>>> +
>>> + if ( !(op_mask & (1 << i)) )
>>> + continue;
>> It occurs from my recent foray into UBSAN that op_mask is 64 bits wide,
>> although it looks like n can be at maximum 16 in this specific case.
>>
>> If nothing else, using (1u << 1) would reduce the size of the UBSAN
>> build, but I expect we're soon going to have subtle bugs when we get to
>> the int8 instructions.
>>
>> Are there current S/G instructions which can take 32 iterations?
> No, S/G insns currently only act on vector elements 32 or 64 bits
> in size, which means 16 or 8 elements per vector max.
In which case we're fine for now.
Acked-by: Andrew Cooper <andrew.coop...@citrix.com>
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