On 12/06/2019 13:54, Pu Wen wrote: > The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and > counter MSRs, hardware configuration MSR, MMIO configuration base address > MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the > PV emulation infrastructure by using the code path of AMD. > > [Rebase over 0cd07414 "x86/cpu: Renumber X86_VENDOR_* to form a bitmap"] > > Signed-off-by: Pu Wen <pu...@hygon.cn> > Acked-by: Jan Beulich <jbeul...@suse.com>
Thanks. I'll commit both of these patches in due course. ~Andrew _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
