On 23/05/2019 13:18, Jan Beulich wrote:
> At least for more recent CPUs, following what BKDG / PPR suggest for the
> BIOS to surface via ACPI we can make ourselves independent of Dom0
> uploading respective data.
>
> Signed-off-by: Jan Beulich <jbeul...@suse.com>
> ---
> TBD: Can we set local_apic_timer_c2_ok to true? I can't seem to find any
> statement in the BKDG / PPR as to whether the LAPIC timer continues
> running in CC6.
This ought to be easy to determine. Given the description of CC6
flushing the cache and power gating the core, I'd say there is a
reasonable chance that the LAPIC timer stops in CC6.
> TBD: We may want to verify that HLT indeed is configured to enter CC6.
I can't actually spot anything which talks about HLT directly. The
closest I can post is CFOH (cache flush on halt) which is an
auto-transition from CC1 to CC6 after a specific timeout, but the
wording suggests that mwait would also take this path.
> TBD: Brian's series specifies .target_residency as 1000 for CC6; may
> want to do so here as well. Question then is whether this value is
> also suitable for the older families.
Well - the PPR does say 400.
> TBD: I guess we could extend this to families older then Fam15 as well.
>
> --- a/xen/arch/x86/acpi/cpu_idle.c
> +++ b/xen/arch/x86/acpi/cpu_idle.c
> @@ -1283,6 +1288,98 @@ long set_cx_pminfo(uint32_t acpi_id, str
> return 0;
> }
>
> +static void amd_cpuidle_init(struct acpi_processor_power *power)
> +{
> + unsigned int i, nr = 0;
> + const struct cpuinfo_x86 *c = ¤t_cpu_data;
> + const unsigned int ecx_req = CPUID5_ECX_EXTENSIONS_SUPPORTED |
> + CPUID5_ECX_INTERRUPT_BREAK;
> + const struct acpi_processor_cx *cx = NULL;
> + static const struct acpi_processor_cx fam17[] = {
> + {
> + .type = ACPI_STATE_C1,
> + .entry_method = ACPI_CSTATE_EM_FFH,
> + .address = 0,
> + .latency = 1,
> + },
> + {
> + .type = ACPI_STATE_C2,
> + .entry_method = ACPI_CSTATE_EM_HALT,
> + .latency = 400,
> + },
> + };
> +
> + if ( pm_idle_save && pm_idle != acpi_processor_idle )
> + return;
> +
> + if ( vendor_override < 0 )
> + return;
> +
> + switch ( c->x86 )
> + {
> + case 0x17:
With Hygon in the mix, this should be expanded to Fam18h.
~Andrew
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