>>> On 27.05.19 at 10:31, <chao....@intel.com> wrote: > Updating microcode is less error prone when caches have been flushed and > depending on what exactly the microcode is updating.
Up to the "and" I understand this sentence, but the rest doesn't really seem to fit. Taking out the good part it seems to me you're saying "Updating microcode is less error prone depending on what exactly the microcode is updating," which - to me at least - doesn't make a hole lot of sense. Should it perhaps be "Updating microcode, depending on what exactly the microcode is updating, may be less error prone when caches have been flushed." (The same could perhaps also be achieved by replacing the "and" by a comma.) > For example, some > of the issues around certain Broadwell parts can be addressed by doing a > full cache flush. > > With parallel microcode update, the cost of this patch is hardly > noticable. Although only BDX with an old microcode needs this fix, we > would like to avoid future issues in case they come by later due to > other reasons. I doubt the "hardly noticable" part, and I'm sure you're also aware of the patch (going on top of your series) to make selecting between serial or parallel application a runtime option. But I'm not going to stand in the way if everyone else thinks this is the way to go; it's just that from previous discussions I didn't get such an impression. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
