>>> On 28.03.19 at 15:43, <jbeul...@suse.com> wrote:
> This is a first preparatory step for enabling x2APIC support also
> for AMD (plus some misc cleanup).
>
> 1: entry: drop unused header inclusions
> 2: APIC: suppress redundant "Switched to ..." messages
> 3: ACPI: also parse AMD IOMMU tables early
> 4: IOMMU: introduce init-ops structure
> 5: IOMMU: abstract Intel-specific iommu_supports_eim()
> 6: IOMMU: abstract Intel-specific iommu_{en,dis}able_x2apic_IR()
> 7: IOMMU: initialize iommu_ops in vendor-independent code
Where applicable, may I ask for an SVM / AMD IOMMU maintainer
ack (or otherwise) please?
Thanks, Jan
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