Hello.
On Mon, 1 Apr 2019, Jan Beulich wrote:
On 31.03.19 at 10:11, <mar...@c-home.cz> wrote:
There is problem in PCI device allocation algorithm (pci_setup()).
Algorithm allocates PCI BAR sorted by size and this allows
mixed allocation of prefetchable and non-prefetchable PCI MEM BAR.
This leads to wrong config of PCI root port (see "Type 1 Configuration
Space Registers (Root Ports)").
Tested with version xen 4.11.1 + "export
OVMF_UPSTREAM_REVISION=ef529e6ab7c31290a33045bb1f1837447cc0eb56"
(embeded commit OVMF does not work (crashed even in Win10.iso and
uncompilable with newer gcc)).
Attached also testing patch.
I agree the problem wants addressing, but I'm afraid the patch is
incomplete: Afaict it won't work if there is a non-prefetchable BAR
larger than the smallest prefetchable one, due to the necessary
extra padding that would need inserting between the two.
I make this patch as proof-of-concept to get it compatible
with OVMF. But I am not aware if OVMF is OK and all other consequences, like:
- allocation aligning as you mention
- PF region to be placed first or last in MMIO hole
- some PCI express documents says that all 64bit MEM BAR must be prefetchable
[ But if I activate "usbversion=3" it generates 64bit MEM BAR but without
prefetchable bit (so PCI_BASE_ADDRESS_MEM_PREFETCH is implicit?) and
actual code allocates MMIO under 4G. But OVMF requires that 64bit MEM BAR
must be placed over 4G (just another problem/BUG). ]
(example -
https://resources.infosecinstitute.com/system-address-map-initialization-x86x64-architecture-part-2-pci-express-based-systems/
)
Also the patch lack your S-o-b and has a couple of style issues
(hard tab used, indentation, lack of blanks inside if(), unnecessary
double use of PCI_BASE_ADDRESS_MEM_PREFETCH).
As to its description - do you perhaps mean "interleaved" instead
of "fragmented" and "not allowed" instead of "not supported"?
Rework/use the patch as needed.
Martin
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