>>> On 21.02.19 at 10:52, <pu...@hygon.cn> wrote: > The Hygon Dhyana CPU supports lots of MSRs(such as perf event select and > counter MSRs, hardware configuration MSR, MMIO configuration base address > MSR, MPERF/APERF MSRs) as AMD CPU does, so add Hygon Dhyana support to the > PV emulation infrastructure by using the code path of AMD. > > Signed-off-by: Pu Wen <pu...@hygon.cn>
Acked-by: Jan Beulich <jbeul...@suse.com> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
