>>> On 15.03.19 at 14:05, <igor.druzhi...@citrix.com> wrote:
> Thanks for clarification. I discussed with Paul - there is definitely
> still a hole in general case where 1st half of the instruction is memory
> and 2nd half is MMIO and the 1st half is changed *to* MMIO. But it's
> hard to deal with these types of accesses without a complete re-write of
> MMIO cache into general insn access cache - so to lift it up to
> linear_{read,write} layer. I hope my understanding is now correct and
> I'll put into the description.Well, mostly. With patch 1 there's no dependency anymore on an access to be page straddling afaict. I.e. the scenarios I gave should apply also to aligned accesses. > Until then the fix should do fine with scenarios we're seeing. Indeed. Jan _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel
